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SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design

Volumn 2006, Issue , 2006, Pages 1-4

Exploiting dynamic and partial reconfiguration for FPGAs - Toolflow, architecture and system integration

(2) Hubner M a,b Becker, J a,b

a IEEE (Germany)

b UNIVERSITY OF KARLSRUHE (Germany)

Author keywords

Designflow; Dynamic and partial reconfiguration; Reconfigurable hardware

Indexed keywords

AUTOMOTIVE; PARTIAL RECONFIGURATION; RUN-TIME;

ADAPTIVE CONTROL SYSTEMS; COMPUTER ARCHITECTURE; LOGIC DESIGN; RESPONSE TIME (COMPUTER SYSTEMS);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33750910879 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (18)

References (10)

1
- 33750897005
- Real-time dynamically run-time reconfiguration for power-/cost-optimized virtex FPGA realizations
- Darmstadt, Sep.
- J. Becker, M. Hübner, M. Ullmann: "Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations", VLSI03, Darmstadt, Sep. 03
- (2003) VLSI03
- Becker, J.¹ Hübner, M.² Ullmann, M.³

2
- 14244269932
- An FPGA run-time system for dynamical on-demand reconfiguration
- Santa Fee
- M. Ullmann, M. Huebner, B. Grimm, J. Becker: "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration", RAW04, Santa Fee
- RAW04
- Ullmann, M.¹ Huebner, M.² Grimm, B.³ Becker, J.⁴

3
- 84856158003
- Power estimation and power measurement of Xilinx Virtex FPGAs: Trade-offs and limitations
- Sao Paulo, Sep.
- J. Becker, M. Hübner, M, Ullmann: "Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-offs and Limitations", SBCCI03, Sao Paulo, Sep. 03
- (2003) SBCCI03
- Becker, J.¹ Hübner, M.² Ullmann, M.³

4
- 14244260572
- Networks on chip: A new paradigm for systems on chip design
- March 3-7, Paris France
- L. Benini, G. De Micheli: "Networks on Chip: A New Paradigm for Systems on Chip Design", Date 02, March 3-7, Paris France
- Date 02
- Benini, L.¹ De Micheli, G.²

5
- 14244258231
- Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
- Brasil
- M. Huebner, T. Becker, J. Becker "Real-Time LUT-Based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration", SBCCI04, Brasil
- SBCCI04
- Huebner, M.¹ Becker, T.² Becker, J.³

6
- 33750919931
- XAPP291
- XAPP291, Xilinx Application note
- Xilinx Application Note

7
- 84965136217
- Core communication interface for FPGAs
- Porto Alegre BRAZIL
- J.C. Palma, A. Vieira de Melo, F. G. Moraes, N. Calazans, "Core Communication Interface for FPGAs", SBCCI02, Porto Alegre BRAZIL
- SBCCI02
- Palma, J.C.¹ De Vieira Melo, A.² Moraes, F.G.³ Calazans, N.⁴

8
- 84860019750
- Novel seamless design-flow for partial and dynamic reconfigurable systems with customized communication structures based on Xilinx Virtex-II FPGAs
- Innsbruck, Austria
- M. Hübner, K. Paulsson, M. Stitz, J. Becker: "Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs", ARCS05, Innsbruck, Austria
- ARCS05
- Hübner, M.¹ Paulsson, K.² Stitz, M.³ Becker, J.⁴

9
- 33750925865
- Partial and dynamically reconfiguration of Xilinx Virtex-II FPGAs
- Antwerp, Belgium
- B. Blodget, C. Bobda, M. Huebner, A. Niyonkuru: "Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs", FPL04, Antwerp, Belgium
- FPL04
- Blodget, B.¹ Bobda, C.² Huebner, M.³ Niyonkuru, A.⁴

10
- 33750922152
- A lightweight approach for embedded reconfiguration of FPGAs
- Munich Germany
- B. Blodget, S. McMillan: "A lightweight approach for embedded reconfiguration of FPGAs", Date03, Munich Germany
- Date03
- Blodget, B.¹ McMillan, S.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.