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Volumn , Issue , 2005, Pages 258-260

SyCE: An integrated environment for system design in systemC

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN ENVIRONMENT; PARSER; SOURCE CODES; VISUALIZATION TOOLS;

EID: 26444589672     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RSP.2005.46     Document Type: Conference Paper
Times cited : (18)

References (13)
  • 2
    • 0038111504 scopus 로고    scopus 로고
    • Functional verification for SystemC descriptions using constraint solving
    • F. Ferrandi, M. Rendine, and D. Scuito. Functional verification for SystemC descriptions using constraint solving. In Design, Automation and Test in Europe, pages 744-751, 2002.
    • (2002) Design, Automation and Test in Europe , pp. 744-751
    • Ferrandi, F.1    Rendine, M.2    Scuito, D.3
  • 3
    • 26444585567 scopus 로고    scopus 로고
    • Efficient hierarchical debugging for property checking
    • DDECS, Bremen
    • G. Fey and R. Drechsler. Efficient hierarchical debugging for property checking. Technical report, DDECS, Bremen, 2005.
    • (2005) Technical Report
    • Fey, G.1    Drechsler, R.2
  • 9
    • 0037774091 scopus 로고    scopus 로고
    • IEEE design and test roundtable on C++-based design
    • May-June
    • R. G. (moderator). IEEE design and test roundtable on C++-based design. IEEE Design & Test of Comp., pages 115-123, 2001. May-June.
    • (2001) IEEE Design & Test of Comp. , pp. 115-123
    • G., R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.