SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin-BOX FD-SOI transistors

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 11, 2006, Pages 2366-2371

  Yamaoka, Masanao ^a,b   Tsuchiya, Ryuta ^b   Kawahara, Takayuki ^a,b  

^a IEEE   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

Back gate bias; Low leakage current; Operating margin; SRAM; Thin buried oxide fully depleted silicon on insulator (thin BOX FD SOI) transistor

Indexed keywords

BACK-GATE BIAS; LOW-LEAKAGE CURRENT; OPERATING MARGIN; THIN BURIED-OXIDE FULLY DEPLETED SILICON-ON-INSULATOR (THIN-BOX FD-SOI) TRANSISTORS;

ELECTRIC POTENTIAL; LEAKAGE CURRENTS; NETWORKS (CIRCUITS); SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 33750827496     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.882891     Document Type: Conference Paper

References (7)

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