A fast dual-field modular arithmetic logic unit and its hardware implementation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 787-790

  Sakiyama, Kazuo ^a   Preneel, Bart ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BIT ERROR RATE; DIGITAL ARITHMETIC; FUNCTION EVALUATION; INTEGER PROGRAMMING; PUBLIC KEY CRYPTOGRAPHY;

ELLIPTIC CURVE; HARDWARE IMPLEMENTATION; HYPERELLIPTIC CURVE CRYPTOGRAPHY; MODULAR ARITHMETIC LOGIC UNIT (MALU);

LOGIC GATES;

EID: 33750735451     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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