Algorithmic/architectural design for H.264/MPEG-4 AVC low-power video codec

2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference

Volumn I, Issue , 2005, Pages 183-186

  Melani, Massimiliano ^a   Fanucci, Luca ^a   Saponara, Sergio ^a  

^a UNIVERSITY OF PISA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTATIONAL METHODS; CONTEXT SENSITIVE GRAMMARS; EMBEDDED SYSTEMS; POWER ELECTRONICS; REAL TIME SYSTEMS;

BIT RATES; CONTEXT AWARE COPROCESSORS; LOW POWER EMBEDDED SYSTEMS; POWER VIDEO CODEC;

OPTICAL DESIGN;

EID: 33750317412     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RME.2005.1543041     Document Type: Conference Paper

References (12)

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