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Volumn 1, Issue , 2003, Pages I133-I136
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A low power VLSI implementation for variable length decoder in MPEG-1 layer III
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
MOTION PICTURE EXPERTS GROUP STANDARDS;
EFFICIENCY REQUIREMENTS;
EFFICIENT ARCHITECTURE;
LOW-POWER CONSUMPTION;
READ/WRITE OPERATIONS;
SIGNAL STATISTICS;
VARIABLE LENGTH CODES;
VARIABLE LENGTH DECODER;
VARIABLE LENGTH DECODING;
DECODING;
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EID: 11244339166
PISSN: 19457871
EISSN: 1945788X
Source Type: Conference Proceeding
DOI: 10.1109/ICME.2003.1220872 Document Type: Conference Paper |
Times cited : (5)
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References (5)
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