Evaluation of on-chip transmission line interconnect using Wire Length Distribution

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 133-138

  Inoue, Junpei ^a   Ito, Hiroyuki ^a   Gomi, Shinichiro ^a   Kyogoku, Takanori ^a   Uezono, Takumi ^a   Okada, Kenichi ^a   Masu, Kazuya ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC LINES; ELECTRIC POWER UTILIZATION;

DELAY TIME; ON CHIPS; RC INTERCONNECTS; RC LINE; TRANSMISSION LINE INTERCONNECT; WIRE LENGTH DISTRIBUTION;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33750061123     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120789     Document Type: Conference Paper

References (6)

1. S. Gomi, K. Nakarnura, H. Ito, K. Okada, and K. Masu, "Differential Transmission Line Interconnect for High Speed and Low Power Global Wiring," Proc. IEEE Custom Integrated Circuits Conference, pp. 325-328, 2004.
2. H. Ito, K. Nakarnura, K. Okada and K. Masu, "High Density Differential Transmission Line Structure on Si USLI", IEICE Transactions on Electronics, Vol. E87-C, No. 6, pp. "942-948, June 2004.
3. J. A. Davis, V. K. De, and J. D. Meindl, "A Stochastic Wire Length Distribution for Gigascale Integration (GSI): Part I: Derivation and Validation," IEEE Trans, on Electron Devices, Vol. 45, No.'3, pp. 580-589, 1998.
4. H. B. Bakoglu, "Circuits, Intreconnections, and Packaging for VLSI." Reading. MA: Addision-Wesley, 1990.
5. S. Wong, T. G. Lee, D. Ma, and C. Chao, "Ari Empirical Three-Dimensional Crossover Capacitance Model for Multilevel Interconnect VLSI Circuits," IEEE Trans. Semiconductor Manufacturing, vol.13, no. 2, pp. 219-227,May 2000.
6. C. K. Cheng, J. Lillis, S. Lin, and N. Chang, "Interconnect Analysis and Synthesis," A Wiley-Interscience Publication., 2000.