Asynchronous processor network - The project of the Polytechnic Institute of Grenoble

Supercomputer

Volumn 12, Issue 3, 1996, Pages 21-26

  Aktouf, Chouki ^a   Latrous, Youssef ^a   Mazare, Guy ^a  

^a LGI IMAG   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33750009442     PISSN: 01687875     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (15)

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2. Dally, W.J. et al, Architecture of a Message-Driven Processor, 14 Symp. on Computer Architecture, 1987, 189-196.
3. Kogge, P.M. EXECUBE - A New Architecture for Scalable MPPs, Proc. of the 1994 International Conference on Parallel Processing, vol. 1, pp. 77-84.
4. Faure, B., S.M. Karabernou, G. Mazare, E. Payan and P. Rubini, Une Architecture Massivement Parallele integree, Annales de Telecommunications, 46, 1-2, 1991.
5. Objois, Ph., Reseau de Cellules Integrees : Mecanisme de Communication Inter-Cellulaire et Application a la Simulation, Ph.D dissertation, INPG, September 1988.
6. Lattard, D., Architecture Massivement Parallele : Un Reseau de Cellules Integre pour la Reconstruction d'Images, Ph.D dissertation, INPG, November 1989.
7. Faure, B. and G. Mazare, A Cellular Architecture Dedicated to Neural Net Emulation, Microprocessing and Microprogramming, Vol. 30, Holland, 1990, pp. 249-256.
8. Latrous, Y. and G. Mazare, Code Distribution in a Parallel Fine Grain Machine, 1st International Workshop on Parallel Processing, Bangalor, India, December 1994, pp. 338-343.
9. Latrous, Y., Gestion Dynamique d'une Architecture Massivement Parallele, Ph.D dissertation, INPG, January 1995.
10. Pierre, M.S., S.W. Yang and D. Cassiday, Functional VLSI Design Verification Methodology for the CM-5 Massively Parallel Supercomputer, Proc. of the International Conference of the Computer Design, 1992, pp. 430-435.
11. Aktouf, C., C. Robach and A. Marinescu, A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1, Proc. of The International Test Conference, October 1995, Washington, 1995, pp. 781-788.
12. Aktouf, C., G. Mazare and C. Robach, Memory Testing in a Massively Parallel Machine, Microprocessing and Microprogramming: the Euromicro Journal, vol. 38, 1-5, September 1993, pp. 245-252.
13. Aktouf, C., C. Robach, J. Johansson and G. Mazare, Functional Testing and Reconfiguration of Massively MIMD Machines, Proc. of the 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 72-79.
14. Aktouf, Ch., Ch. Robach and G. Mazare, Fault-tolerant Routing Algorithms for a Massively Parallel Machine, 22th International Conference on Parallel Processing, August 1994, Vol. 1, pp. 246-249.
15. Aktouf, C., C. Robach and G. Mazare, Reconfiguration of a Massively Parallel Architecture, Euromicro, Liverpool, England, September 1994, pp. 689-696.