-
3
-
-
0030104367
-
Programmable active memo-ries: Reconfigurable systems come of age
-
Nol, March
-
J.E.Vuillemin, P. Bertin, D.Roncin, M.Shand, H.H. Touati and P.Boucard, "Programmable Active Memo-ries: Reconfigurable Systems Come of Age, IEEE Trans on VLSI Systems, Vol.4, Nol, March 1996, pp 56-68.
-
(1996)
IEEE Trans on VLSI Systems
, vol.4
, pp. 56-68
-
-
Vuillemin, J.E.1
Bertin, P.2
Roncin, D.3
Shand, M.4
Touati, H.H.5
Boucard, P.6
-
4
-
-
0031605446
-
-
Hawaii, January
-
A.Postula, D.Abramson, Z.Fang, P.Logothetis, A Comparison of High Level Synthesis and Register Transfer Level Design Techniques for Custom Computing Machines, HICSS'98, Hawaii, January 1998.
-
(1998)
A Comparison of High Level Synthesis and Register Transfer Level Design Techniques for Custom Computing Machines, HICSS'98
-
-
Postula, A.1
Abramson, D.2
Fang, Z.3
Logothetis, P.4
-
5
-
-
0030168210
-
Multiskewing - A novel technique for optimal parallel memory access
-
June
-
Deb-A., "Multiskewing - A Novel Technique For Optimal Parallel Memory Access," IEEE Trans. Parallel-and-Distributed-Systems. Vol.7, No.6, June 1996, pp.595604.
-
(1996)
IEEE Trans. Parallel-and-Distributed-Systems
, vol.7
, Issue.6
, pp. 595604
-
-
Deb, A.1
-
7
-
-
0024752697
-
On access and alignment of data in a parallel processor
-
27 Oct.
-
De-Lei-Lee, "On access and alignment of data in a parallel processor," Information-Processing-Letters., Vol. 33,No.1;27 Oct. 1989; pp.11-14.
-
(1989)
Information-Processing-Letters
, vol.33
, Issue.1
, pp. 11-14
-
-
De-Lei, L.1
-
8
-
-
0343327560
-
High-bandwidth interleaved memories for vector processors - A simulation study
-
Jan.
-
Sohi-G.S., "High-bandwidth interleaved memories for vector processors - a simulation study," IEEE-Trans.-on-Computers. Vol.42, No.l; Jan. 1993; pp.34-44.
-
(1993)
IEEE-Trans.-on-Computers
, vol.42
, Issue.1
, pp. 34-44
-
-
Sohi, G.S.1
-
9
-
-
0026122803
-
Conflict-gree vector access using a dynamic storage scheme
-
March
-
Harper, D.T., Linebarger, D.A., "Conflict-Gree Vector Access Using a Dynamic Storage Scheme," IEEE Trans, on Computers, Vol. 40, No. 3, March 1991, pp. 276283.
-
(1991)
IEEE Trans, on Computers
, vol.40
, Issue.3
, pp. 276283
-
-
Harper, D.T.1
Linebarger, D.A.2
-
10
-
-
0022083698
-
The structare of periodic storage schemes for parallel memories
-
June
-
Wijshoff-HAG; van-Leeuwen-J, "The Structare Of Periodic Storage Schemes For Parallel Memories," lEEE-Trans.-on-Computers. Vol.C-34, No.6; June 1985; pp.501-505.
-
(1985)
LEEE-Trans.-on-Computers.
, vol.C-34
, Issue.6
, pp. 501-505
-
-
Wijshoff, H.A.G.1
Van-Leeuwen, J.2
-
12
-
-
85051145029
-
Background me-meory area estimation for multi-dimensional signal processing systems
-
F.Balasa , F.Cathoor and H.De Man, Background Me-meory Area Estimation for Multi-dimensional Signal Processing Systems, IEEE Trans, on CAD, , Vol 14 , 1995.
-
(1995)
IEEE Trans, on CAD
, vol.14
-
-
Balasa, F.1
Cathoor, F.2
De Man, H.3
-
13
-
-
0029475549
-
A memory selection algorithm for high-performance pipelines
-
Bakshi-S; Gajski-DD S. , "A Memory Selection Algorithm for High-Performance Pipelines", Proceedings EURO-DAC'95, 1995, pp. 124-129.
-
(1995)
Proceedings EURO-DAC'95
, pp. 124-129
-
-
Bakshi, S.1
Gajski, D.D.S.2
-
14
-
-
0028728521
-
A new technique for exploiting regularity in data path synthesis
-
M.Aloqeely, C.Y.R.Chen, "A new Technique for Exploiting Regularity in Data Path Synthesis", Proc. of EURO-DAC-94, 1994, pp394-399.
-
(1994)
Proc. of EURO-DAC-94
, pp. 394-399
-
-
Aloqeely, M.1
Chen, C.Y.R.2
-
15
-
-
0028712353
-
Hardware/software partitioning and minimizing memory interface traffic
-
A. Jantsch, P. Ellervee, J. Oberg, A. Hemani, H. Ten-hunen, "Hardware/Software Partitioning and Minimizing Memory Interface Traffic", Proc. of EURO-DAC-94, pp226-231, 1994.
-
(1994)
Proc. of EURO-DAC
, vol.94
, pp. 226-231
-
-
Jantsch, A.1
Ellervee, P.2
Oberg, J.3
Hemani, A.4
Ten-Hunen, H.5
-
17
-
-
33747492020
-
Definition and solution of the memory packing problem
-
Nov.
-
D.Karchmer, and J.Rose, "Definition and Solution of the Memory Packing Problem," Proc. of ICCAD, pp. 53-58, Nov. 1994.
-
(1994)
Proc. of ICCAD
, pp. 53-58
-
-
Karchmer, D.1
Rose, J.2
-
18
-
-
0031099182
-
Synthesis of applications-specific memory designs
-
March
-
Herman Schmit and Donald E. Thomas, "Synthesis of Applications-Specific Memory Designs," IEEE Trans, on VLSI Systems, Vol. 5, No. 1, pp. 101-111, March, 1997.
-
(1997)
IEEE Trans, on VLSI Systems
, vol.5
, Issue.1
, pp. 101-111
-
-
Schmit, H.1
Thomas, D.E.2
-
20
-
-
85051108213
-
-
Dept. of Computer Science and Electrical Engineering, The University of Queensland, Ausltralia
-
S. Chen, A. Postula, Interleaved Memory Optimization with Periodic Storage Scheme Synthesis, Internal Report, Dept. of Computer Science and Electrical Engineering, The University of Queensland, Ausltralia, 1998.
-
(1998)
Interleaved Memory Optimization with Periodic Storage Scheme Synthesis, Internal Report
-
-
Chen, S.1
Postula, A.2
-
21
-
-
85051108213
-
-
S.Chen, A.Postula, A.Hemani, Interleaved Memory Optimization with Periodic Storage Scheme Synthesis, APCHDL'98, Korea, 1998.
-
(1998)
Interleaved Memory Optimization with Periodic Storage Scheme Synthesis, APCHDL'98, Korea
-
-
Chen, S.1
Postula, A.2
Hemani, A.3
-
23
-
-
85051104544
-
-
The Programmable Logic Data Book, Xilinx
-
The Programmable Logic Data Book, Xilinx, 1994, http://vww.xilinx.com.
-
(1994)
-
-
|