High density, low cost packaging and interconnect technology

2nd 1998 IEMT/IMC Symposium

Volumn 1998-April, Issue , 1998, Pages 10-17

  Garrou, P ^a  

^a MCNC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; MICROELECTRONICS;

ALTERNATIVE TECHNOLOGIES; INTERCONNECT SCHEMES; INTERCONNECT TECHNOLOGY; LARGE-AREA PROCESSING; LOW-COST PACKAGING; MICROVIAS; NEW TECHNOLOGIES; SEAMLESS HIGH OFF-CHIP CONNECTIVITIES;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33749893207     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMTIM.1998.704499     Document Type: Conference Paper

References (10)

1. The National Technoloqv Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, p. 63 (1994).
2. ICE Corp , Tempe Az.
3. Y. Tsukada, S. Tsuchida, Y. Mashimoto, "Surface Laminar Circuits and Flip Chip Pkging", Proceed. 42nd ECTC, 1992, p. 2227.
4. G. Rinne, "Solder Bump Methods for Flip Chip Packaging", Proceed. 47'h ECTC, 1997, p. 240.
5. Y. Nakamura, et. al. , "Advanced LSI Packaging Using Stud Bump Bonding Technology" , Proceed. Int MCM Conference, Denver, 1995, 302.
6. T. Ogashiwa, et. al., "Direct Solder Technique on an AI Pad and Its Reliability", Japanese Journal of Applied Physics, part 1, vol. 31, 1992, p. 761.
7. P. Elanius, "Flex on Cap Solder Paste Bumping", Proceed. ECTC, 1997, p. 248
8. J. Kloeser, et. al., "Fine Pitch Stencil Printing of Pb/Sn and Pb Free Solders for Flip Chip", Proceed ECTC, 1997, p 254
9. D. Mis, G. Rinne, P. Deane, G. Adema, "Flip Chip Production Experience", Proceed ISHM, 1996, p. 291.
10. J. Simon, et. al. 'I A Comparison of Flip Chip Technology with Chip Size Packages", Proceed. IEPS, 1995, p. 665.