Bounded model checking of concurrent data types on relaxed memory models: A case study

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4144 LNCS, Issue , 2006, Pages 489-502

  Burckhardt, Sebastian ^a   Alur, Rajeev ^a   Martin, Milo M K ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONCURRENT ENGINEERING; DATA REDUCTION; DATA STORAGE EQUIPMENT; MATHEMATICAL MODELS; SECURITY OF DATA;

BOUNDED VERIFICATION METHOD; CONCURRENT ALGORITHMS; MULTITHREADED PROGRAMS; RELAXED MEMORY MODELS;

COMPUTER PROGRAMMING;

EID: 33749866867     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11817963_45     Document Type: Conference Paper

References (31)

1. H. Sutter and J. Larus. Software and the concurrency revolution. ACM Queue, 3(7):54-62, 2005.
2. M. Herlihy. Wait-free synchronization. ACM Trans. Program. Lang. Syst., 13(1):124-149, 1991.
3. G. L. Peterson. Concurrent reading while writing. ACM Trans. Program. Lang. Syst., 5(1):46-55, 1983.
4. L. Lamport. Concurrent reading and writing. Commun. ACM, 20(11):806-811, 1977.
5. S. V. Adve and K. Gharachorloo. Shared memory consistency models: a tutorial. Computer, 29(12):66-76, 1996.
6. L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comp., C-28(9):690-691, 1979.
7. T. Elmas, S. Tasiran, and S. Qadeer. VYRD: verifying concurrent programs by runtime refinement-violation detection. In Programming Language Design and Implementation (PLDI), pages 27-37, 2005.
8. E. Clarke, D. Kroening, and F. Lerda. A tool for checking ANSI-C programs. In Tools and Algorithms for the Construction and Analysis of Systems (TACAS), LNCS 2988, pages 168-176. Springer, 2004.
9. Y. Yang, G. Gopalakrishnan, and G. Lindstrom. Memory-model-sensitive data race analysis. In International Conference on Formal Engineering Methods (ICFEM), LNCS 3308, pages 30-45. Springer, 2004.
10. G. Gopalakrishnan, Y. Yang, and H. Sivaraj. QB or not QB: An efficient execution verification tool for memory orderings. In Computer-Aided Verification (CAV), LNCS 3114, pages 401-413, 2004.
11. M. M. Michael and M. L. Scott. Simple, fast, and practical non-blocking and blocking concurrent queue algorithms. In Principles of Distributed Computing (PODC), pages 267-275, 1996.
12. V. Vafeiadis, M. Herlihy, T. Hoare, and M. Shapiro. Proving correctness of highly-concurrent linearisable objects. In Principles and Practice of Parallel Programming (PPoPP), pages 129-136, 2006.
13. I. Rabinovitz and O. Grumberg. Bounded model checking of concurrent programs. In Computer-Aided Verification (CAV), LNCS 3576, pages 82-97. Springer, 2005.
14. E. Yahav and M. Sagiv. Automatically verifying concurrent queue algorithms. Electr. Notes Theor. Comput. Sci., 89(3), 2003.
15. M. P. Herlihy and J. M. Wing. Linearizability: a correctness condition for concurrent objects. ACM Trans. Program. Lang. Syst., 12(3):463-492, 1990.
16. S. Park and D. L. Dill. An executable specification, analyzer and verifier for RMO (relaxed memory order). In Symposium on Parallel Algorithms and Architectures (SPAA), pages 34-41, 1995.
17. D. L. Dill, S. Park, and A. G. Nowatzyk. Formal specification of abstract memory models. In Symposium on Research on Integrated Systems, pages 38-52. MIT Press, 1993.
18. S. Savage, M. Burrows, G. Nelson, P. Sobalvarro, and T. Anderson. Eraser: A dynamic data race detector for multithreaded programs. ACM Trans. Comp. Sys., 15(4):391-411, 1997.
19. B. Frey. PowerPC Architecture Book v2.02. International Business Machines Corporation, 2005.
20. D. L. Weaver and T. Germond, editors. The SPARC Architecture Manual Version 9. PTR Prentice Hall, 1994.
21. Compaq Computer Corporation. Alpha Architecture Reference Manual, 4th edition, January 2002.
22. International Business Machines Corporation. z/Architecture Principles of Operation, first edition, December 2000.
23. Y. Yang, G. Gopalakrishnan, G. Lindstrom, and K. Slind. Analyzing the Intel Itanium memory ordering rules using logic programming and SAT. In Correct Hardware Design and Verification Methods (CHARME), LNCS 2860, pages 81-95. Springer, 2003.
24. R. Alur, K. McMillan, and D. Peled. Model-checking of correctness conditions for concurrent objects. In Logic in Computer Science (LICS), pages 219-228, 1996.
25. R. C. Steinke and G. J. Nutt. A unified theory of shared memory consistency. J. ACM, 51(5): 800-849, 2004.
26. Y. Yang, G. Gopalakrishnan, G. Lindstrom, and K. Slind. Nemos: A framework for axiomatic and executable specifications of memory consistency models. In International Parallel and Distributed Processing Symposium (IPDPS), 2004.
27. D. Shasha and M. Snir. Efficient and correct execution of parallel programs that share memory. ACM Trans. Program. Lang. Syst., 10(2):282-312, 1988.
28. X. Fang, J. Lee, and S. P. Midkiff. Automatic fence insertion for shared memory multiprocessing. In International Conference on Supercomputing (ICS), pages 285-294, 2003.
29. C. von Praun, T. Cain, J. Choi, and K. Ryu. Conditional memory ordering. In International Symposium on Computer Architecture (ISCA), 2006.
30. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Design Automation Conference (DAC), pages 530-535, 2001.
31. M. Martin, D. Sorin, H. Cain, M. Hill, and M. Lipasti. Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. In International Symposium on Microarchitecture (MICRO), pages 328-337, 2001.