A high-speed hardware architecture for universal message authentication code

IEEE Journal on Selected Areas in Communications

Volumn 24, Issue 10, 2006, Pages 1831-1839

  Yang, Bo ^b   Karri, Ramesh ^b   McGrew, David A ^a,c  

^a IEEE

^b POLYTECHNIC UNIVERSITY   (United States)

^c CISCO SYSTEMS   (United States)

Author keywords

Divide and concatenate; Performance optimization; Universal hash functions; Universal message authentication code (UMAC)

Indexed keywords

DIVIDE-AND-CONCATENATE; PERFORMANCE OPTIMIZATION; UNIVERSAL HASH FUNCTIONS; UNIVERSAL MESSAGE AUTHENTICATION CODE (UMAC);

CODES (SYMBOLS); COMPUTER HARDWARE; COPYRIGHTS; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; PROBABILITY;

COMPUTER ARCHITECTURE;

EID: 33749856204     PISSN: 07338716     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSAC.2006.877133     Document Type: Article

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