A novel low power and high performance 14 transistor CMOS full adder cell

Journal of Applied Sciences

Volumn 6, Issue 9, 2006, Pages 1978-1981

  Vigneswaran, T ^a   Mukundhan, B ^a   Reddy, P Subbarami ^a  

^a SRM INSTITUTE OF SCIENCE AND TECHNOLOGY   (India)

Author keywords

Arithmetic circuit; Full adder; Low power; Very large scale integration (VLSI)

Indexed keywords

AGGRESSIVE DESIGNS; ARITHMETIC CIRCUIT; DIGITAL SIGNAL PROCESSORS (DSP); FULL ADDER CELLS; FULL ADDERS; LOW POWER; TRANSISTOR COUNT; VERY LARGE-SCALE INTEGRATION;

LOW POWER ELECTRONICS; MOLECULAR BIOLOGY; SIGNAL PROCESSING;

ADDERS;

EID: 33749647012     PISSN: 18125654     EISSN: 18125662     Source Type: Journal    
DOI: 10.3923/jas.2006.1978.1981     Document Type: Article

References (6)

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