Completion-detection techniques for asynchronous circuits

IEICE Transactions on Information and Systems

Volumn E80-D, Issue 3, 1997, Pages 344-349

  Grass, Eckhard ^a   Bartlett, Viv ^a   Kale, Izzet ^a  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CIRCUIT THEORY; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; DETECTOR CIRCUITS; ENCODING (SYMBOLS);

ASYNCHRONOUS CIRCUITS; BOUNDED DELAY; COMPLETION DETECTION; DOUBLE RAIL CODING; MICROPIPELINE; SELF TIMING;

LOGIC CIRCUITS;

EID: 0031100824     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

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2. S. Haucic "Asynchronous design methodologies: An overview," Proc. IEEE, vol.83, no.l, pp.69-93, 1995.
3. M E. Dean, D.L. Dill, and VI. Horowitz, "Self-timed logic using current-sensing completion detection (CSCD)," Journal of VLSI Signal Proc., vol.7, no.i, pp.7-16, 1994.
4. ME. Dean, T.E. Williams, and D.L. Dill, "Efficient selftiming with level-encodac 2-phase dual-rail (LEDR)," MIT Conference on Advanced Research in VLSI, March 1991.
5. O.A. Izosimov, I.I. Shagurin, and V'.V. Tsylyov, "Physical approach to CMOS self-timing," Electronics Letters, vol.26, pp. 1835-1836, 1990.
6. E. Grass and S. Jones, "Asynchronous circuits based on multiple localised Current-sensing completion detection," Proc. 2nd Working Com". Asynchronous Design Methodologies (London), pp.170-! 77, May 1995.
7. T.H.-Y Meng, R.W. Broaerson, and D.G. Messerschmidt, "Automatic synthesis of asynchronous circuits from highlevel specifications," IEEE Trans. Computer-Aided Design, -vol.8, no.il, pp.li85 -1205, ,989.
8. E. Grass, R.C.S. Morling, and I. Kale, "Activitymonitoring completion-detection (AMCD): A new single rail approach to achieve self-liming," Proc. of the IEEE 2nii Internat. Symp. Advanceo Research in Asynchronous Circuits and Systems, A;zu (Japan), pp. 1-43-149, Varch 1996.