μComplexity: Estimating processor design effort

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2005, Pages 209-218

  Bazeghi, Cyrus ^a   Mesa Martinez, Francisco J ^a   Renau, Jose ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST ESTIMATION; HDL CODE; NONLINEAR MIXED-EFFECTS MODEL; PROCESSOR DESIGN;

CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; FLIP FLOP CIRCUITS; PROBLEM SOLVING; PRODUCT DESIGN; PRODUCTIVITY; REGRESSION ANALYSIS; RESOURCE ALLOCATION;

MICROPROCESSOR CHIPS;

EID: 33749413981     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.37     Document Type: Conference Paper

References (23)

1. A.J. Albrecht. Measuring Application Development Productivity. In SHARE/GUIDE IBM Applications Development Symposium, Oct 1979.
2. Semiconductor Industry Association. International Technology Roadmap for Semiconductors (ITRS), 2002.
3. B. Boehm. Software Engineering Economics. Prentice-Hall, 1981.
4. Altera Corporation. Stratix II Device Family Literature, 2005. http://www.altera.com/products/devices/stratix2/.
5. E.L. Crow and K. Shimizu. Lognormal Distributions: Theory and Application. Dekker, 1988.
6. M. Davidian and M.D. Giltinan. Nonlinear Models for Repeated Measurement Data. Chapman & Hall, 1995.
7. T. DeMarco and T. Lister. Peopleware Productive Projects and Teams. Dorset House Publishing, 1999.
8. A.J. Drake, T.D. Basso, S.M. Gold, K.L. Kraver, P.N. Parakh, C.R. Gauthier, P. S. Stetson, and R.B. Brown. CGaAs PowerPC FXU. In International Conference on Design Automation, pages 730-735, New York, NY, USA, 2000. ACM Press.
9. S. Fenstermaker, D. George, A. B. Kahng, St. Mantik, and B. Thielges. METRICS: A System Architecture for Design Process Optimization. In International Conference on Design Automation, pages 705-710, Jun 2000.
10. W. Fornaciari, F. Salice, and D.P. Scarpazza. Early Estimation of the Size of VHDL Projects. In International Conference on Hardware/Software Codesign and System Synthesis, pages 207-212, Oct 2003.
11. J. Gaisler, S. Habine, and E. Catovic. GRLIB IP Library User's Manual, 2005. http://www.gaisler.com.
12. R. Goodall, D. Fandel, A. Allan, P. Landler, and H. R. Huff. Long Term Productivity Mechanisms of the Semiconductor Industry. www.sematech.org, 2002.
13. J.P. Hoffmann. Generalized Linear Models. Pearson, 2004.
14. SPARC International Inc. The SPARC Architecture Manual Version 8, 1992. http://www.sparc.com.
15. Synopsys Inc. Design Compiler Product Information, 2005. http://www.synopsys.com.
16. Synplicity Inc. SynplifyPro Product Information, 2005. http://www.synplicity.com.
17. P. Kudva, B. Curran, S.K. Karandikar, M. Mayo, S. Carey, and S.S. Sapatnekar. Early Performance Prediction. In Workshop on Complexity-Effective Design, Jun 2005.
18. P. Kudva, A. Sullivan, and W. Dougherty. Metrics for Structural Logic Synthesis. In International Conference on Computer-Aided Design, pages 551-556, Nov 2002.
19. R.C. Littell, G.A. Milliken, W.W. Stroup, and R.D. Wolfinger. SAS System for Mixed Models. SAS Publishing, 1996.
20. T. Little. Value Creation and Capture: A Model of the Software Development Process. IEEE Software, 21(3):48-53, 2004.
21. Numetrics Management Systems. Key Performance Indicators of IC Development Capability-A Framework. Technical report, Numetrics Management Systems, Inc., 2005. http://www.numetrics.com.
22. The R Development Core Team. The R Reference Manual - Base Package. Network Theory Limited, 2005.
23. N.J. Wang, J. Quek, T.M. Rafacz, and S.J. Patel. Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. In International Conference on Dependable Systems and Networks. IEEE Computer Society, Jun 2004.