A theoretical discussion on performance limits of CMOS charge pumps

Proceedings of the 2005 European Conference on Circuit Theory and Design

Volumn 2, Issue , 2005, Pages 35-38

  Cabrini, A ^a   Gobbi, L ^a   Torelli, G ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; ELECTRIC CHARGE; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; ENERGY EFFICIENCY;

CMOS CHARGE PUMPS; PARASITIC CAPACITANCES; POWER EFFICIENCY; VOLTAGE GAIN;

CMOS INTEGRATED CIRCUITS;

EID: 33749045290     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECCTD.2005.1522986     Document Type: Conference Paper

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