Efficiency comparison between doubler and dickson charge pumps

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1891-1894

  Baderna, D ^a   Cabrini, A ^a   Torelli, G ^a   Pasotti, M ^b  

^a UNIVERSITY OF PAVIA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE PUMP; CHARGE PUMP STRUCTURE; CLOCK FREQUENCY; CMOS TECHNOLOGY; DICKSON CHARGE PUMP; DOUBLER; MAIN PARAMETERS; POWER EFFICIENCY; STORAGE CAPACITANCE; TRIPLE WELL; VOLTAGE DOUBLER;

CMOS INTEGRATED CIRCUITS;

PUMPS;

EID: 33646408442     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464981     Document Type: Conference Paper

References (5)

1. J.F. Dickson: "On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique", IEEE J. of Solid- State Circuits, vol.SC-11, no. 3, p. 374, Jun. 1976.
2. T. Tanzawa: "A Dynamic Analysis of the Dikson Charge Pump", IEEE J. of Solid-State Circuits, vol.32, no. 8, p. 1231-1240, Aug. 1997.
3. P. Favrat, P. Deval and M.J. Declercq: "A high-efficiency CMOS voltage doubler", IEEE J. of Solid-State Circuits, vol.33, no. 3, pp. 410-416, March 1998.
4. G. Palumbo, D. Pappalardo and M. Gaibotti,: "Charge-pump circuits: power-consumption optimization", IEEE Trans. on Circuits and Systems, vol.49, no. 11, pp. 1535-1542, Nov. 2002.
5. R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti and P.L. Rolandi: "Power efficient charge pump in deep submicron standard CMOS technology", IEEE J. of Solid-State Circuits, vol.38, no. 6, pp.1068-1071, Jun. 2003.