Low voltage sensing techniques and secondary design issues for sub-90nm caches

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 413-416

  Smha, Manoj ^a   Hsu, Steven ^b   Alvandpour, Atila ^b   Burleson, Wayne ^a   Krishnamurthy, Ram ^b   Borkar, Shekhar ^b  

^a University of Massachusetts   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BITLINE CAPACITANCE; CMOS TECHNOLOGY; CURRENT SENSE AMPLIFIERS; SENSE AMPLIFIER; SENSING SCHEMES; SENSING TECHNIQUES; SPEED IMPROVEMENT; SUPPLY VOLTAGES;

CAPACITANCE; CHARGE TRANSFER; CMOS INTEGRATED CIRCUITS; SEMICONDUCTOR STORAGE;

SENSORS;

EID: 33748529546     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257160     Document Type: Conference Paper

References (9)

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3. Blalock. N.T. et al. A high-speed clamped bit-line current-mode sense amplifier IEEE JSSC 542-548.
4. Izumikawa. M. et al. A 400MHz, 300mW, 8Kb CMOS RAM Macro with A Current-Sensing Scheme 1994 595-598 IEEE CICC.
5. Wicht. B. et al. Analysis and compensation of bittine multiplexer in sram current sense amplifiers IEEE JSSC 2001.
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8. S. Thompson et. al, "A 90nm Logic Technology Featuring 50nm Strained-Silicon Transistors, 7 Layers Copper Interconnect, Low-K ILD, and lmm2 SRAM Cell", IEDM Tech Digest, pp. 61-64, 2002.
9. T. Sakurai, "High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage" 1SCAS, vol. 3, pp. 1487-1490, May 1993.