The liberty simulation environment: A deliberate approach to high-level system modeling

ACM Transactions on Computer Systems

Volumn 24, Issue 3, 2006, Pages 211-249

  Vachharajani, Manish ^a,b   Vachharajani, Neil ^a,c   Penry, David A ^a,d   Blome, Jason A ^a,e   Malik, Sharad ^a,c   August, David I ^a,c  

^a PRINCETON UNIVERSITY   (United States)

^b UCB 450   (United States)

^c Princeton University   (United States)

^d Department of Electrical and Computer Engineering   (United States)

^e UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Component reuse; Liberty Simulation Environment (LSE); Simulator construction; Structural modeling

Indexed keywords

COMPONENT REUSE; LIBERTY SIMULATION ENVIRONMENT (LSE); SIMULATOR CONSTRUCTION; STRUCTURAL MODELING;

COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COMPUTER SIMULATION; DIGITAL INSTRUMENTS; MATHEMATICAL MODELS;

SYSTEMS ENGINEERING;

EID: 33748306072     PISSN: 07342071     EISSN: 07342071     Source Type: Journal    
DOI: 10.1145/1151690.1151691     Document Type: Article

References (28)

1. AUSTIN, T. 1997. A user's and hacker's guide to the SimpleScalar Architectural Toolset (for toolset release 2.0). Go online to http://www.cs.virginia.edu/~skadron/cs654/slides/hack_guide.pdf.
2. BLOME, J., VACHHARAJANI, M., VACHHARAJANI, N., AND AUGUST, D. I. 2003. The Liberty Simulation Environment as a pedagogical tool. In Proceedings of the 2003 Workshop on Computer Architecture Education (WCAE).
3. BURGER, D. AND AUSTIN, T. M. 1997. The SimpleScalar tool set version 2.0. Tech. Rep. 97-1342, Department of Computer Science, University of Wisconsin-Madison, Madison, WI.
4. CAIN, H. W., LEPAK, K. M., SCHWARTZ, B. A., AND LIPASTI, M. H. 2002. Precise and accurate processor simulation. In Proceedings of the Fifth Workshop on Computer Architecture Evaluation Using Commercial Workloads.
5. CHAREST, L. AND ABOULHAMID, E. M. 2002. A VHDL/SystemC comparison in handling design reuse. In Proceedings of 2002 International Workshop on System-on-Chip for Real-Time Applications.
6. COE, P., HOWELL, F., IBBETT, R., AND WILLIAMS, L. 1998. A hierarchical computer architecture design and simulation environment. ACM. Trans. Model. Comput. Sim. 8, 4 (Oct.), 431-446.
7. DESIKAN, R., BURGER, D., AND KECKLER, S. W. 2001. Measuring experimental error in microprocessor simulation. In Proceedings of the 28th International Symposium on Computer Architecture (ISCA). 266-277.
8. DOUCET, F., OTSUKA, M., SHUKLA, S., AND GUPTA, R. 2002. An environment for dynamic component composition for efficient co-design. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE).
9. DOUCET, F., SHUKLA, S., AND GUPTA, R. 2003. Typing abstractions and management in a component framework. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC). 115-122.
10. EMER, J., AHUJA, P., BORCH, E., KLAUSER, A., LUK, C.-K., MANNE, S., MUKHERJEE, S. S., PATIL, H., WALLACE, S., BINKERT, N., ESPASA, R., AND JUAN, T. 2002. Asim: A performance model framework. IEEE Comput. 0018-9162, 68-76.
11. GIBSON, J., KUNZ, R., OFELT, D., HOROWITZ, M., HENNESSY, J., AND HEINRICH, M. 2000. FLASH vs. (simulated) FLASH: Closing the simulation loop. In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 49-58.
12. HALAMBI, A., GRUN, P., GANESH, V., KHARE, A., DUTT, N., AND NICOLAU, A. 1999. EXPRESSION. A language for architecture exploration through compiler/simulator retargetability. In Proceedings of the European Conference on Design, Automation and Test (DATE).
13. JANNECK, J. W., LEE, E. A., LIU, J., LIU, X., NEUENDORFFER, S., SACHS, S., AND XIONG, Y. 2001. Disciplining heterogeneity - the Ptolemy approach. In ACM SIGPLAN 2001 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES).
14. KICZALES, G., LAMPING, J., MENDHEKAR, A., MAEDA, C., LOPES, C., LOINGTIER, J.-M., AND IRWIN, J. 1997. Aspect-oriented programming. In Proceedings of the 11th European Conference for Object-Oriented Programming (ECOOP). 220-242.
15. MISHRA, P., DUTT, N., AND NICOLAU, A. 2001. Functional abstraction driven design space exploration of heterogeneous programmable architectures. In Proceedings of the International Symposium on System Synthesis (1SSS). 256-261.
16. ÖNDER, S. AND GUPTA, R. 1998. Automatic generation of microarchitecture simulators. In Proceedings of the IEEE International Conference on Computer Languages. 80-89.
17. OPEN SYSTEMC INITIATIVE (OSCI). 2001. Functional Specification for SystemC 2.0. Available online at http://www.systemc.org.
18. PEES, S., HOFFMANN, A., ŽIVOJNOVIC, V., AND MEYR, H. 1999. LISA - machine description language for cycle-accurate models of programmable DSP architectures. In Proceedings of the ACM / IEEE Design Automation Conference (DAC). 933-938.
19. PENRY, D. AND AUGUST, D. I. 2003. Optimizations for a simulator construction system supporting reusable components. In Proceedings of the 40th Design Automation Conference (DAC).
20. PENRY, D. A., VACHHARAJANI, M., AND AUGUST, D. I. 2005. Rapid development of a flexible validated processor model. In Proceedings of the 2005 Workshop on Modeling, Benchmarking, and Simulation (MOBS).
21. SISKA, C. 1998. A processor description language supporting retargetable multi-pipeline dsp program development tools. In Proceedings of the 11th International Symposium on System Synthesis (ISSS).
22. SWAMY, S., MOLIN, A., AND CONVOT, B. 1995. 00-VHDL: Object-oriented extensions to VHDL. IEEE Comput. 28, 10 (Oct.), 18-26.
23. THE LIBERTY RESEARCH GROUP. 2003. Web site:http://www.liberty-research.org/Software/LSE.
24. VACHHARAJANI, M. 2004. Microarchitectural modeling for design-space exploration. Ph.D. dissertation, Department of Electrical Engineering, Princeton University, Princeton, NJ.
25. VACHHARAJANI, M., VACHHARAJANI, N., AND AUGUST, D. I. 2004a. The Liberty Structural Specification Language: A high-level modeling language for component reuse. In Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design, and, Implementation (PLDI). 195-206.
26. VACHHARAJANI, M., VACHHARAJANI, N., MALIK, S., AND AUGUST, D. I. 2004b. Facilitating reuse in hardware models with enhanced type inference. In Proceedings of the 2004 Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
27. VACHHARAJANI, M., VACHHARAJANI, N., PENRY, D. A., BLOME, J. A., AND AUGUST, D. I. 2002. Microarchitectural exploration with Liberty. In Proceedings of the 35th International Symposium on Microarchitecture (MICRO). 271-282.
28. XIONG, Y. 2002. An extensible type system for component based design. Ph.D. dissertation. Electrical Engineering and Computer Sciences, University of California, Berkeley, CA.