Automated hot-spot fixing system applied for metal layers of 65 nm logic devices

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6283 I, Issue , 2006, Pages

  Kobayashi, Sachiko ^a   Kyoh, Suigen ^a   Kotani, Toshiya ^a   Tanaka, Satoshi ^a   Inoue, Soichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Design rule; DfM; Hot spot fixing; Layout modification

Indexed keywords

COMPUTER SIMULATION; DATA ACQUISITION; LITHOGRAPHY; MICROPROCESSOR CHIPS; OPTICAL RESOLVING POWER; SYSTEMS ANALYSIS;

DESIGN RULE; DFM; HOT SPOT FIXING; LAYOUT MODIFICATION;

LOGIC DEVICES;

EID: 33748083375     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.681852     Document Type: Conference Paper

References (5)

1. T. Kotani et al, "Yield enhanced layout generation by new design for manufacturability", Proc. SPIE Vol. 5379 (2003)
2. S. Inoue, "Patterning friendly design methodology for 65nm and beyond technology nodes", 8th International Forum on Semiconductor Technology IFST, June 2005, JAPAN
3. S. Inoue et al, "Total hot spot management from design rule definition to silicon fabrication", Electronic Design Processes Workshop EDP, April 2003, Monterey CA
4. T. Kotani et al, "Development of hot spot fixer", Proc. SPIE Vol. 6156 (2006), to be published
5. S. Kyoh et al, "Lithography oriented DfM for 65nm and beyond", Proc. SPIE Vol. 6156 (2006), to be published