Yield enhanced layout generation by new design for manufacturability (DfM) flow

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5379, Issue , 2004, Pages 128-138

  Kotani, Toshiya ^a   Tanaka, Satoshi ^a   Nojima, Shigeki ^a   Hashimoto, Koji ^a   Inoue, Soichi ^a   Mori, Ichiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Compaction tool; Design rule; DfM; Hot spot; Lithography design; Manufacturability check; OPC; RET; Yield enhancement

Indexed keywords

DESIGN FOR TESTABILITY; FEEDBACK; LITHOGRAPHY; OPTICAL RESOLVING POWER; PATTERN RECOGNITION; PROCESS ENGINEERING; ULSI CIRCUITS;

COMPACTION TOOLS; DESIGN FOR MANUFACTURABILITY (DFM); DESIGN RULES; HOT SPOTS; LITHOGRAPHY DESIGNS; MANUFACTURABILITY CHECKS; OPTICAL PROXIMITY CORRECTION (OPC); RESOLUTION ENHANCEMENT TECHNIQUE (RET); YIELD ENHANCEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 2942666041     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.536254     Document Type: Conference Paper

References (2)

1. S. Inoue, T. Kotani, S. Nojima, S. Tanaka, K. Hashimoto and I. Mori: Electronic Design Processes (EDP) Workshop (2003).
2. T. Kotani, K.Ichikawa, T.Urakami, S.Nojima, S.Kobayashi, Y.Oikawa, S.Tanaka, A.Ikeuchi, K.Suzuki and S.Inoue: Proc. SPIE Vol. 5130 (2003) 628