Characterization and noise analysis of a 12-bit current steering digital-to-analog converter

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 204-207

  Lahoz, Tomás ^a   Barajas, Enrique ^a   González, José Luis ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT STEERING DIGITAL-TO-ANALOG CONVERTERS; DI/DT NOISE; HIGH-ACCURACY; HIGH-SPEED; NOISE ANALYSIS; POWER SUPPLY LINE; SUBSTRATE NOISE;

HYBRID COMPUTERS;

EID: 33747824118     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464560     Document Type: Conference Paper

References (7)

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2. Patrik Larsson, "Resonance and Damping in CMOS Circuits with On-Chip Decoupling Capacitance," IEEE Tran. on Circuits and Systems-I: Fund. Theory and Applications, vol. 45, No 8, 1998, pp. 849-858.
3. José Luis González, and Eduard Alarcón, Current-Steering High-Speed D/A Converters for Communications, in A. Rodríguez-Vázquez, et al., ed., CMOS Telecom Data Converters, Kluwer Academic Publishers, Boston, 2003.
4. Howard W. Johnson, Martin Graham, High-Speed Digital Design, A Handbook of Black Magic, Prentice Hall, New Jersey, 1993.
5. A. vand den Bosch, M. Steyaert, and W. Sansen, "SFDR-Bandwidth Limitations for High-Speed High Resolution Current Steering CMOS D/A Converters," Proc. of the IEEE Inl.l Conference on Electronics, Circuits and Systems, 1999, pp. 1193-1196.
6. J. Bastos, A. M. Marques, M. S. J. Steyaert, and Willy Sansen, "A 12- bit Intrinsic Accuracy High-Speed CMOS DAC," IEEE J. of Solid-State Circuits, Vol. 33, No. 12, 1998, pp. 1959-1969.
7. J.L. González, E. Alarcón, "Clock-Jitter Induced Distortion in High- Speed CMOS Switched-Current Segmented Digital-to-Analog Converters," Proc. of the IEEE Intl. Symposium on Circuits and Systems, 2001, Vol. I, pp. 512-515.