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Volumn 2006, Issue , 2006, Pages 59-66

Congestion modeling for reconfigurable inter-processor networks

Author keywords

Congestion; Interconnection network; Prediction; Reconfiguration

Indexed keywords

COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS; PACKET NETWORKS; QUEUEING NETWORKS; TELECOMMUNICATION TRAFFIC;

EID: 33747307821     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/1117278.1117292     Document Type: Conference Paper
Times cited : (2)

References (8)
  • 6
    • 0002435274 scopus 로고    scopus 로고
    • Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of the system architecture
    • D. A. B. Miller and H. M. Ozaktas. Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of the system architecture. Journal of Parallel and Distributed Computing, 41(1):42-52, 1997.
    • (1997) Journal of Parallel and Distributed Computing , vol.41 , Issue.1 , pp. 42-52
    • Miller, D.A.B.1    Ozaktas, H.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.