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Volumn 2005, Issue , 2005, Pages 142-147

Novel FPGA-based implementation of median and weighted median filters for image processing

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; IMAGE PROCESSING; MATHEMATICAL TRANSFORMATIONS; RESOURCE ALLOCATION; THROUGHPUT;

EID: 33746933845     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515713     Document Type: Conference Paper
Times cited : (63)

References (11)
  • 5
    • 0025415006 scopus 로고
    • Design and implementation of a general-purpose median filter unit in CMOS VLSI
    • M. Karaman, L. Onural, and A. Atalar, "Design and implementation of a general-purpose median filter unit in CMOS VLSI," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 505-13, 1990.
    • (1990) IEEE Journal of Solid-state Circuits , vol.25 , Issue.2 , pp. 505-513
    • Karaman, M.1    Onural, L.2    Atalar, A.3
  • 11
    • 0029544569 scopus 로고
    • Two-dimensional median filter algorithm for parallel reconfigurable computers
    • L. Hayat, M. Fleury, and A. Clark, "Two-dimensional median filter algorithm for parallel reconfigurable computers," IEE Proc. Vision, Image and Signal Processing, vol. 142, no. 6, pp. 345-50, 1995.
    • (1995) IEE Proc. Vision, Image and Signal Processing , vol.142 , Issue.6 , pp. 345-350
    • Hayat, L.1    Fleury, M.2    Clark, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.