Network-on-Chip based runtime systems for dynamically reconfigurable hardware;Network-on-Chip basierende Laufzeitsysteme für dynamisch rekonfigurierbare Hardware

Lecture Notes in Informatics (LNI), Proceedings - Series of the Gesellschaft fur Informatik (GI)

Volumn P-41, Issue , 2004, Pages 185-194

  Hecht, Ronald ^a   Timmermann, Dirk ^a   Kubisch, Stephan ^a   Zeeb, Elmar ^a  

^a UNIVERSITY OF ROSTOCK   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33745596831     PISSN: 16175468     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. [Br97] Brebner, G.: The Swappable Logic Unit: A Paradigm for Virtual Hardware. In: Proc. of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines. S. 77–86. Napa Valley, California. 1997.
3. Marescaux, T., Bartic, A., Verkest, D., Vernalde, S., und Lauwereins, R.: Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGAs. In: LNCS. volume 2438 of Proc. 12th Int. Conf. on Field-Programmable Logic and Applications. S. 795–805. Springer. 2002.
4. Marescaux, T., Mignolet, J.-Y., Bartic, A., Moffat, W., Verkest, D., Vernalde, S., und Lauwereins, R.: Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. In: Proc. 13th Int. Conf. on Field-Programmable Logic and Applications. S. 595–605. 2003.
5. [Sh03a] Shashi, K.: On Packet Switched Networks for On-chip Communication. In: Networks on Chip. S. 85–106. Kluwer Academic Publishers. 2003.
6. [SH03b] Soininen, J.-P. und Heusala, H.: A Design Methodology for NoC-based Systems. In: Networks on Chip. S. 19–38. Kluwer Academic Publishers. 2003.