Architectural enhancements for network congestion control applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 6, 2006, Pages 609-615

  Lee, Byeong Kil ^a,b   John, Lizy Kurian ^a,c   John, Eugene ^a,d  

^a IEEE   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c The University of Texas at Austin   (United States)

^d University of Texas at San Antonio   (United States)

Author keywords

Congestion control; Hardware acceleration; Network processor; Parallelism

Indexed keywords

HARDWARE ACCELERATION; NETWORK PROCESSOR; PARALLELISM; RANDOM EARLY DETECTION (RED);

ALGORITHMS; MATHEMATICAL MODELS; NETWORK PROTOCOLS; PACKET NETWORKS; PROGRAM PROCESSORS; QUEUEING NETWORKS; REDUCED INSTRUCTION SET COMPUTING; SCHEDULING; THROUGHPUT;

CONGESTION CONTROL (COMMUNICATION);

EID: 33746925229     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878211     Document Type: Article

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