The design and analysis of a DLL-based frequency synthesizer for UWB application

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 6, 2006, Pages 1245-1251

  Lee, Tai Cheng ^a,b   Hsiao, Keng Jan ^b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Delay locked loops; Frequency multiplier; Phase noise

Indexed keywords

DELAY LOCKED LOOPS (DLL); DISCRETE-TIME MODEL; FREQUENCY MULTIPLIERS; PHASE NOISE;

BANDWIDTH; BROADBAND NETWORKS; CMOS INTEGRATED CIRCUITS; DISCRETE TIME CONTROL SYSTEMS; MATHEMATICAL MODELS; PHASE LOCKED LOOPS;

FREQUENCY SYNTHESIZERS;

EID: 33746658762     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.874353     Document Type: Article

References (10)

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