A DLL-based frequency multiplier for MBOA-UWB system

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 42-45

  Lee, Tai Cheng ^a   Hsiao, Keng Jan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Delay locked loops; Frequency multiplier; UWB

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; FREQUENCY SYNTHESIZERS; SPURIOUS SIGNAL NOISE;

DELAY LOCKED LOOPS; FREQUENCY MULTIPLIERS; SIDEBAND MAGNITUDE; UWB;

BROADBAND NETWORKS;

EID: 33644655407     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469329     Document Type: Conference Paper

References (4)

1. G. Chien and P. R. Gray, "A 900-MHz Local Oscillator Using a DLL-Based Frequency Multiplier Technique for PCS Applications," IEEE J. Solid-State Circuits, vol. 35, pp. 1996-1999, Dec. 2000.
2. J. Zhuang, Q. Du and Tad Kwasniewski, "A -107dBc, 10kHz Carrier Offset 2-GHz DLL-Based Frequency Synthesizer," Proc. of Custom Integrated Circuits Conf., 2003, pp. 301-304.
3. R. Farjad-Rad, W. Dally, H.-T. Ng, A. Senthinathan, M.-J. Lee, R. Rathi and J. Poulton, "A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips," IEEE J. Solid-State Circuits, vol. 37, pp. 1804-1812, Dec. 2002.
4. S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi and H. K. Lim, "A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL," IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.