A-107dBc, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 301-304

  Zhuang, Jingcheng ^a   Du, Qingjin ^a   Kwasniewski, Tad ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY DOMAIN ANALYSIS; FREQUENCY SYNTHESIZERS; JITTER; PHASE COMPARATORS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

DELAY LOCKED LOOP; EDGE COMBINING CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 0242696127     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. David S. Korn, "The effect of phase noise and spurs on coherent communications performance" MILCOM '95, Conference Record, IEEE. Nov. 1995, Vol. 1, pp. 383-387
2. David J. Foley, Michael P. Flynn. "CMOS DLL based 2V, 3.2ps jitter, 1GHz clock synthesizer and temperature compensated tunable oscillator" Proc. IEEE Custom Integrated Circuits Conference, 2000, pp. 371-374
3. Sheng Ye, Lars Jansson, Lan Galton, "A multiple-crystal interface PLL with VCO realignment to reduce phase noise" Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International, Vol. 1, 2002, pp. 78-447