Automatic task scheduling / loop unrolling using dedicated RTR controllers in coarse grain reconfigurable architectures

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Benoit, Pascal ^a   Torres, Lionel ^a   Sassatelli, Gilles ^a   Robert, Michel ^a   Cambon, Gaston ^a  

^a LIRMM   (France)

Author keywords

Digital signal and image processing; Reconfigurable architectures; Run time reconfiguration; System on chip

Indexed keywords

(DYNAMIC HARDWARE MULTIPLEXING; RECONFIGURABLE ARCHITECTURES; RUN TIME RECONFIGURATION; SYSTEM-ON-CHIP;

CONTROL EQUIPMENT; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER UTILIZATION; IMAGE PROCESSING; SCHEDULING;

PARALLEL PROCESSING SYSTEMS;

EID: 33746286968     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.119     Document Type: Conference Paper

References (12)

1. Stephen Brown and J. Rose, "Architecture of FPGAs and CPLDs: A Tutorial", IEEE Design and Test of Computers, Vol. 13, No. 2, pp. 42-57, 1996.
2. R. Hartenstein (embedded tutorial): A Decade of Reconfigurable Computing: a Visionary Retrospective; DATE 2001, Int'l Conference on Design Automation and Testing in Europe - and Exhibit, Munich, Germany - March 12-15, 2001
3. Le Moullec Y., Heller D., Diguet J-Ph. et Philippe J-L., "Estimation du parallélisme au niveau système pour l'exploration de l'espace de conception de systèmes enfouis", Technique et Science Informatiques, Vol. 22, Lavoisier Hennes-Science publications, no3/2003, p. 315-349
4. Krishnaprasad S., "Uses and abuses of Amdahl's law", Journal of Computing Sciences in Colleges, Vol. 17, Issue 2, décembre 2001, p. 288-293
5. Tullsen D.M. et al., "Simultaneous Multithreading: Maximizing on-chip parallelism", In Proc. Of the 22nd. annual, Intl. Symp. On Computer Architecture, June 1995, pp. 392-403
6. Codina J. M., Llosa J. et Antonio Gonzalez, "A Comparative Study of Modulo Scheduling Techniques", Proc. of the 26th International Conference on Supercomputing, USA, New York City, Juin 2002, p.97-106
7. S. Singh and P. James-Roxby, Lava and JBits: From HDL to Bitstreams in Seconds, IEEE Symposium on FPGAs for Custom Computing Machines, April 2001
8. D.R. Curd, "Partial reconfiguration of RocketIO Preemphasis and differential Swing Control Attributes", Xilinx, 2003
9. th Design Automation and Teste in Europe (DATE'03), pp. 399-400, Germany, 2003
10. Wirthlin M. J. and Hutchings B. L., "Improving Functional Density Using Run-Time Circuit Reconfiguration", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 6, June 1998, p. 247-256
11. Sassatelli G., Torres L., Galy J., Cambon G., and Diou C., "The systolic ring: A dynamically reconfigurable architecture for embedded systems", In International Workshop on Field Programmable Logic and Applications (FPL 01), Lecture Notes in Computer Science 2147, 2001, p. 409-419
12. G. Sassatelli, "Architectures reconfigurables dynamiquement pour les Systèmes sur Puce", PhD Thesis, University de Montpellier II, 2002