IPSec implementation on Xilinx Virtex-II Pro FPGA and its application

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Lu, Jing ^a   Lockwood, John ^a  

^a WASHINGTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AES ENCRYPTION; HARDWARE LOGIC IMPLEMENTS; SOFTWARE FUNCTION; SOFTWARE PROCESSING;

COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA PROCESSING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746274125     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.262     Document Type: Conference Paper

References (15)

1. FREESWAN. Online:http://www. freeswan.org.
2. KAME. Online:http://www.kame.net.
3. OPENBSD. Online:http://www.openbsd.org.
4. FIPSP-180-1, Apr. 1995.
5. FIPS-197: Advanced Encryption Standard (AES). Online:http://csrc.nist.gov/encryption/aes/, Feb. 2001.
6. Virtex-11 Pro Platform FPGA Handbook, Oct. 2002.
7. F. Braun, J. W. Lockwood, and M. Waldvogel. Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware. Technical Report WU-CS-01-10, Washington University in Saint Louis, Department of Computer Science, June 2001.
8. S. Dharmapurikar, P. Krishnamurthy, T. Sproull, and J. Lockwood. Deep Packet Inspection using Parallel Bloom Filters. In IEEE Micro, Vol. 24, No. 1, pp. 62-69, Jan. 2003.
9. J. W. Lockwood, J. S. Turner, and D. E. Taylor. Field Programmable Port Extender (FPX) for Distributed Routing and Queuing. In ACM International Symposium on Field Programmable Gate Arrays (FPGA'2000), Monterey, CA, USA, Feb. 2000.
10. J. W. Lockwood, C. Zuver, C. Neely, J. Moscola, S. Dharmapurikar, and D. Lim. An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall. In Field Programmable Logic and Applications (FPL'2003), Lisbon, Portugal, 2003.
11. J. Moscola, J. Lockwood, R. P. Loui, and M. Pachos. Implementation of a Content-Scanning Module for an Internet Firewall. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'2003), Napa, CA, USA, Apr. 2003.
12. R. Rivest. The MD5 Message-Digest Algorithm, RFC 1321. MIT LCS and RSA Data Security, Inc., Apr. 1992.
13. D. Schuehler and J. Lockwood. A Modular System for FPGA-based TCP Flow Processing in High-Speed Networks. In 14th International Conference on Field Programmable Logic and Applications (FPL'2004), Springer LNCS 3203, Antwerp, Belgium, Aug. 2004.
14. D. E. Taylor, J. S. Turner, J. W. Lockwood, T. S. Sproull, and D. B. Parlour. Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers. In Computer Networks, Vol. 28, Issue 3, pp. 295-310, Feb. 2002.
15. I. Verbauwhede, P. Schaumont, and H. Kuo. Design and Performance Testing of a 2.29 Gbps Rijndael Processor. In IEEE J. SolidState Circuits, Vol. 38, no. 3, pp. 569-572, 2003.