Optimization of contact hole lithography for 65-nm node logic LSI

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6154 III, Issue , 2006, Pages

  Setta, Yuji ^a   Futatsuya, Hiroki ^a   Sagisaka, Atsushi ^a   Chijimatsu, Tatsuo ^a   Minami, Takayoshi ^a   Sugimoto, Fumitoshi ^a   Ishikawa, Seiichi ^a   Asai, Satoru ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

DOF; MEF; OAI; OPC; PSM; RET; SRAF

Indexed keywords

LIGHTING; OPTICAL ENGINEERING; OPTICAL RESOLVING POWER; OPTIMIZATION; PATTERN RECOGNITION; PHOTOLITHOGRAPHY;

DEPTH OF FOCUS (DOF); LSI; MEF; OAI; OPC; PSM; RET; SUB-RESOLUTION ASSIST FEATURE (SRAF);

LSI CIRCUITS;

EID: 33745804702     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.656224     Document Type: Conference Paper

References (4)

1. V. Liberman et al., "Controlled Contamination Studies in 193-nm Immersion Lithography", Optical Microlithography XVIII, proceeding of SPIE vol. 5754, p. 148-153, 2005.
2. Christine Wallace et al., "Optimization of Resist Shrink Techniques for Contact Holes and Metal Trench ArF Lithography at the 90nm Technology Node", Advances in Resist Technology and Processing XXI, proceeding of SPIE vol. 5376, p. 238-244, 2004.
3. Stephen Hsu et al., "Feasibility Study of Double Exposure Lithography for 65 nm & 45nm node", Photomask and Next-Generation Lithography Mask Technology XII, proceeding of SPIE vol. 5853, p. 252-264, 2005.
4. Sang-Wook Kim et al., "Fulfillment of model-based OPC for contact patterns in the 60-nm level logic device", Optical Microlithography XVII, proceeding of SPIE vol. 5377, p. 1157- 1164, 2004.