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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3019, Issue , 2004, Pages 36-41

Configurable microprocessor array for DSP applications

(3) Maslennikow, Oleg a Shevtshenko, Juri a Sergyienko, Anatoli a

a KOSZALIN UNIVERSITY OF TECHNOLOGY (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; HARDWARE; LINEAR EQUATIONS; MATRIX ALGEBRA; MICROPROCESSOR CHIPS; RECONFIGURABLE HARDWARE; REDUCED INSTRUCTION SET COMPUTING;

DESIGN PROCESS; DSP APPLICATION; HIGH THROUGHPUT; LINEAR EQUATION SYSTEM; MICROPROCESSOR ARCHITECTURES; RISC ARCHITECTURE; TOEPLITZ MATRICES; VHDL MODELING;

INTEGRATED CIRCUIT DESIGN;

EID: 33745796618 PISSN: 03029743 EISSN: 16113349 Source Type: Book Series
DOI: 10.1007/978-3-540-24669-5_5 Document Type: Article

Times cited : (4)

References (8)

1
- 0032166897
- The flexibility of configurable computing
- Villasenor, J., Hutchings, B.: The flexibility of configurable computing. IEEE Signal Processing Magazine, vol. 15, (1998), 67-84.
- (1998) IEEE Signal Processing Magazine , vol.15 , pp. 67-84
- Villasenor, J.¹ Hutchings, B.²

2
- 84947572014
- Implementation of Givens QR Decomposition in FPGA
- Springer
- Sergyienko, A., Maslennikov, O.: Implementation of Givens QR Decomposition in FPGA. Lecture Notes in Computer Science, vol.2328, Springer, (2002), 453-459.
- (2002) Lecture Notes in Computer Science , vol.2328 , pp. 453-459
- Sergyienko, A.¹ Maslennikov, O.²

3
- 35048900576
- VHDL-Model of Ultrafast Microcontroller 8051
- Poland
- Lepekha, V., Sergyienko, A., Kaniewski, J.: VHDL-Model of Ultrafast Microcontroller 8051. Proc. 3-d Region. Conf. Reprogramowalne Uklady Cyfrowe, RUC'2000, Poland,(2000), 35-41.
- (2000) Proc. 3-d Region. Conf. Reprogramowalne Uklady Cyfrowe, RUC'2000 , pp. 35-41
- Lepekha, V.¹ Sergyienko, A.² Kaniewski, J.³

4
- 35048884180
- Configurable microcontroller array
- Warszaw, Poland
- Maslennikov, O., Shevtshenko, Ju., Sergyienko, A.: Configurable microcontroller array. Proc. of the 3-d Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC'2002, Warszaw, Poland, (2002), 47-49.
- (2002) Proc. of the 3-d Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC'2002 , pp. 47-49
- Maslennikov, O.¹ Shevtshenko, Ju.² Sergyienko, A.³

5
- 35048889016
- Kiev, Diasoft, (In Russian)
- Sergyienko, A.: VHDL for computer development. Kiev, Diasoft, (2003), (In Russian).
- (2003) VHDL for Computer Development
- Sergyienko, A.¹

6
- 35048862376
- Mapping regular algorithms into processor arrays using software pipelining
- Poland
- Sergyienko, A., Kaniewski, J., Maslennikov, O., Wyrzykowski, R.: Mapping regular algorithms into processor arrays using software pipelining. Proc. of the 1-st Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC' 1998, Poland, (1998), 197-200.
- (1998) Proc. of the 1-st Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC' 1998 , pp. 197-200
- Sergyienko, A.¹ Kaniewski, J.² Maslennikov, O.³ Wyrzykowski, R.⁴

7
- 0004687628
- A Method for the Structural Synthesis of Pipelined Array Processors
- Poland
- Kanevski, Ju.S., Sergienko, A., Piech, H.: A Method for the Structural Synthesis of Pipelined Array Processors. Proc. of the 1-st Int. Conf. on Parallel Proc. and Appl. Math., PRAM'94, Poland, (1994), 100-109.
- (1994) Proc. of the 1-st Int. Conf. on Parallel Proc. and Appl. Math., PRAM'94 , pp. 100-109
- Kanevski, Ju.S.¹ Sergienko, A.² Piech, H.³

8
- 28244469617
- Prentice Hall, Englewood Cliffs
- Kung, S.Y.: VLSI processor arrays. Prentice Hall, Englewood Cliffs, (1988).
- (1988) VLSI Processor Arrays
- Kung, S.Y.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.