Configurable microcontroller array

Proceedings - International Conference on Parallel Computing in Electrical Engineering, PARELEC 2002

Volumn , Issue , 2002, Pages 47-49

  Maslennikov, O ^a   Shevtshenko, J ^b   Sergyienko, A ^b  

^a KOSZALIN UNIVERSITY OF TECHNOLOGY   (Poland)

^b ZAPORIZHZHYA NATIONAL TECHNICAL UNIVERSITY   (Ukraine)

Author keywords

Clocks; Frequency; Genetic algorithms; Hardware; Image processing; Logic arrays; Microcontrollers; Neural networks; Pattern recognition; Programmable logic arrays

Indexed keywords

ALGORITHMS; CLOCKS; COMPUTATION THEORY; COMPUTER HARDWARE; CONTROLLERS; GENETIC ALGORITHMS; HARDWARE; MICROCONTROLLERS; NETWORK ARCHITECTURE; NEURAL NETWORKS; PATTERN RECOGNITION;

APPLICATION PROGRAMMING; CLOCK FREQUENCY; CONFIGURABLE HARDWARE; FREQUENCY; HIGH SPEED; LOGIC ARRAYS; PROGRAMMABLE LOGIC ARRAY;

IMAGE PROCESSING;

EID: 35048884180     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PCEE.2002.1115196     Document Type: Conference Paper

References (8)

1. J. Villasenor, B. Hutchings, "The flexibility of configurable computing," IEEE Signal Processing Magazine , vol. 15, pp.67-84, May 1998.
2. A. Sergyienko, O. Maslennikov, "Implementation of Givens QR Decomposition in FPGA," Lecture Notes in Computer Science, Springer, vol.2328, pp.453-459, 2002.
3. V.Lepekha, A.M.Sergyienko, J.Kaniewski, "VHDL-Model of Ultrafast Microcontroller 8051," Proc. 3-d Region. Conf. "Reprogramowalne Uklady Cyfrowe, RUC'2000", Szczecin, Poland, pp.35-41, 2000.
4. "DR8051 8-bit RISC microcontroller". Data sheet. Available at www.dcd.com.pl/.
5. B.Schmidt, M.Schimmler, H. Schroeder, "Morphological Hough Transform on the Instruction Systolic Array," Proc. Euro-Par'97. pp.798-806, 1997.
6. P.M.Embree and D.Danieli, "C++ Algorithms for Digital Signal Processing," Prentice Hall, 579p. 1999.
7. A. Calardo, "Comms warm a bit to reconfigurable processor," EE Times, March, 30, 2001.
8. P. Clarce. "Beefly parallel processor packs 128 cores," EE Times. Sept., 10, 2001.