A programmable DSP core for baseband processing

3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005

Volumn 2005, Issue , 2005, Pages 403-406

  Tell, Eric ^a   Nilsson, Anders ^a   Liu, Dake ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; LOCAL AREA NETWORKS; SILICON;

BASEBAND PROCESSING; COMPLEX DATA; DATA MEMORY SIZE; WIRELESS LOCAL AREA NETWORK (WLAN);

PROGRAM PROCESSORS;

EID: 33745790301     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2005.1496739     Document Type: Conference Paper

References (5)

1. J. Kneip et.al. Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications, IECICE Trans. Electron., vol.E85-C, N0.2 February 2002.
2. J. Glossner et al, A Software-Defined Communications Baseband Chip, IEEE Communications Magazine, January 2003.
3. S. Rajagopal et al. A Programmable Baseband Processor Design for Software Defined Radios, Proc. Midwest Symposium on Circuits and Systems (MWSCAS 2002), p. III-413 - III-416,
4. http://www.sdrforum.org
5. Anders Nilsson, Eric Tell, Dake Liu, An Accelerator Structure for Multi-Standard Programmable Baseband Processors, proc. of IASTED Intl. Multi-Conf. on Wireless and Optical Com., pp 644-649, July 2004