Using reconfigurable OPC to improve quality and throughput of sub-100nm IC manufacturing

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6154 III, Issue , 2006, Pages

  Morse, Richard D ^a   LoPresti, Pat ^a   Corbett, Kevin ^a  

^a Aprio Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FULL-CHIP OPC; LRC ERRORS; OPC CONVERGENCE; OPC TECHNOLOGY;

CONVERGENCE OF NUMERICAL METHODS; ERROR CORRECTION; MICROPROCESSOR CHIPS; OPTIMIZATION; PHOTOLITHOGRAPHY; PROBLEM SOLVING; RANDOM PROCESSES;

INTEGRATED CIRCUITS;

EID: 33745789834     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.656708     Document Type: Conference Paper

References (5)

1. Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration Xin Wang, Mark Pillof, Hongbo Tang, and Clive Wu Proc. SPIE 5756, 361 (2005)
2. Applying reconfigurable RET across process window to create more robust manufacturing designs Mark Laurance, Abhishek Vikram, Melody Ma, William Volk, Melissa Anderson, Scott Andrews, Bo Su, Hong Du, and Gaurav Verma Proc. SPIE 5992, 59921X (2005)
3. Full-chip lithography simulation and design analysis: how OPC is changing IC design Chris Spence Proc. SPIE 5751, 1 (2005)
4. Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM) William Howard, Jaione Tirapu Azpiroz, Yalin Xiong, Chris Mack, Gaurav Verma, William Volk, Harold Lehon, Yunfei Deng, Rui-fang Shi, James Culp, and Scott Mansfield Proc. SPIE 5756, 61 (2005)
5. Cost of ownership reduction for OPC development and production Chi-Min Yuan, Bob Jarvis, Kevin D. Lucas, Robert Boone, Ruiqi Tian, and Alfred Reich Proc. SPIE 5377, 1121 (2004)