Full-chip lithography manufacturability check for yield improvement

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6156, Issue , 2006, Pages

  Huang, Yongfa ^a   Tseng, Edward ^a   Lin, Benjamin Szu Min ^a   Yu, Chun Chi ^a   Wang, Chien Ming ^b   Liu, Hua Yu ^b  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b Brion Technologies   (United States)

Author keywords

Lithography manufacturability; Lithography simulation; Mask error enhancement factor (MEEF); Model accuracy; Process window; Process window modeling

Indexed keywords

LITHOGRAPHY MANUFACTURABILITY; LITHOGRAPHY SIMULATION; MASK ERROR ENHANCEMENT FACTOR (MEEF); MODEL ACCURACY; PROCESS WINDOW; PROCESS WINDOW MODELING;

COMPUTER SIMULATION; MATHEMATICAL MODELS; PROCESS CONTROL; PRODUCT DESIGN;

PHOTOLITHOGRAPHY;

EID: 33745774333     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.656401     Document Type: Conference Paper

References (3)

1. nd Annual BACUS Symposium on Photomask Technology, Vol.4889, pp. 187-196, 2002
2. Kohji Hashimoto, Takeshi Ito, Takahiro Ikeda, Shigeki Nojima and Soichi Inoue "Model-based PPC Verification Methodology with Two-dimensional Pattern Feature Extraction", Proc. SPIE Symposium, Vol.5040 pp112
3. Yu Cao, Yen -Wen Lu, Luoqi Chen, and Jun Ye, "Optimized Hardware and Software for Fast, Full Chip Simulation" Proc. SPIE Vol. 5754, pp 407-414, 2005.