Strain enhanced DC-RF performance of 0.13 m nMOSFETs on flexible plastic substrate

Electronics Letters

Volumn 42, Issue 14, 2006, Pages 827-829

  Chin, A ^a   Kao, H L ^a   Kao, C H ^b   Liao, C C ^a   Tseng, Y Y ^a   Chi, C C ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b Takming College   (Taiwan)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; PERFORMANCE; PLASTICS; SILICON NITRIDE; SPURIOUS SIGNAL NOISE; STRAIN;

FLEXIBLE PLASTIC SUBSTRATE; SATURATION CURRENT; STRAIN ENHANCEMENT; TENSILE STRAIN;

MOSFET DEVICES;

EID: 33745769562     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20061035     Document Type: Article

References (10)

1. Ohguro, T.: et al. ' Improvement of high resistivity substrate for future mixed analog-digital application ', Symp. on VLSI Tech. Dig., 2002, p. 158-159
2. Yu, D.S.: et al. ' Narrow-band band-pass filters on silicon substrates at 30GHz ', IEEE MTT-S Int. Microw. Symp. Dig., 2004, 3, p. 1467-1470
3. Chin, A.: et al. ' RF passive devices on Si with excellent performance close to ideal devices designed by electro-magnetic simulation ', IED Int. Electron Device Mtg Tech. Dig., December 8-10 2003, p. 375-378
4. Chan, K.T.: et al. ' Low RF loss and noise of transmission lines on Si substrates using an improved ion implantation process ', IEEE MTT-S Int. Microw. Symp. Dig., 2003, 2, p. 963-966
5. Kao, H.L.: et al. ' Very low noise RF nMOSFETs on plastic by substrate thinning and wafer transfer ', IEEE Microw. Wirel. Compon. Lett., 2005, 15, (11), p. 757-759
6. Takayama, T.: et al. ' A CPU on a plastic film substrate ', Symp. on VLSI Tech. Dig., June 2004, p. 230-231
7. Ghani, T.: et al. ' A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors ', IED Int. Electron Device Mtg Tech. Dig., December 8-10 2003, p. 11.6.1-11.6.3
8. Zhao, W.: et al. ' Partially depleted SOI MOSFETs under uniaxial tensile strain ', IEEE Trans. Electron Devices, 2004, 54, p. 317-323
9. Kao, H.L.: et al. ' Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout ', RF IC Symp. Dig., June 2005, p. 157-160
10. Paul, D.J.: ' Si/SiGe heterostructures: from material and physics to devices and circuits ', Semicond. Sci. Technol., 2004, 19, p. R75-R108