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Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6156, Issue , 2006, Pages

Using design intent to qualify and control lithography manufacturing

(10) Vasek, Jim a Wilkinson, Bill a Reich, Al a Garza, Cesar a Zhao, Joyce b Wiley, Jim b Poyastro, Moshe c Troy, Brian c Nehmadi, Youval c Abraham, Zamir d

a FREESCALE SEMICONDUCTOR INC (United States)

b Brion Technologies Inc (United States)

c APPLIED MATERIALS INC (United States)

d Applied Materials Inc Israel (Israel)

Author keywords

CD SEM; Full chip modeling; GDS II; Hot spot; OPC; Process control; Process window; Simulation

Indexed keywords

COMPUTER SIMULATION; DATABASE SYSTEMS; MANUFACTURE; MATHEMATICAL MODELS; MEASUREMENT THEORY; PROCESS CONTROL; PRODUCT DESIGN; SCANNING ELECTRON MICROSCOPY; SILICON WAFERS; STRUCTURAL DESIGN; TWO DIMENSIONAL;

CD SEM; FULL-CHIP MODELING; GDS-II; HOT SPOTS; OPC; PROCESS WINDOW;

LITHOGRAPHY;

EID: 33745600452 PISSN: 0277786X EISSN: None Source Type: Conference Proceeding
DOI: 10.1117/12.656856 Document Type: Conference Paper

Times cited : (14)

References (5)

1
- 17944378769
- Characterization of optical proximity correction features
- N. Sullivan, Ed.
- J. Allgair, M. Ivy, K. Lucas, J. Sturtevant, R. Elliott, C. Mack, C. MacNaughton, J. Miller, M. Pochkowski, M. Preil, J. Robinson, F. Santos, "Characterization of optical proximity correction features," Metrology, Inspection, and Process Control for Microlithography XV, N. Sullivan, Ed., Vol. 4344, pp. 200-207, 2001
- (2001) Metrology, Inspection, and Process Control for Microlithography XV , vol.4344 , pp. 200-207
- Allgair, J.¹ Ivy, M.² Lucas, K.³ Sturtevant, J.⁴ Elliott, R.⁵ Mack, C.⁶ MacNaughton, C.⁷ Miller, J.⁸ Pochkowski, M.⁹ Preil, M.¹⁰ Robinson, J.¹¹ Santos, F.¹²

2
- 27644494160
- Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era
- M. Brodsky, S. Halle, V. Jophlin-Gut, L. Liebmann, D. Samuels, G Crispo, K. Nafisi, V. Ramani, I. Peterson, "Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era," IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pp. 64-71, 2005
- (2005) IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop , pp. 64-71
- Brodsky, M.¹ Halle, S.² Jophlin-Gut, V.³ Liebmann, L.⁴ Samuels, D.⁵ Crispo, G.⁶ Nafisi, K.⁷ Ramani, V.⁸ Peterson, I.⁹

3
- 33745792959
- Through-process window resist modeling strategies for the 65 nm node
- J. T. Weed, P. Martin, Eds.
- th Annual BACUS Symposium on Photomask Technology, J. T. Weed, P. Martin, Eds., Vol. 5992, pp. 408-417, 2005
- (2005) th Annual BACUS Symposium on Photomask Technology , vol.5992 , pp. 408-417
- Borjon, A.¹ Belledent, J.² Trouiller, Y.³ Patterson, K.⁴ Lucas, K.⁵ Couderc, C.⁶ Sundermann, F.⁷ Urbani, J.-C.⁸ Baron, S.⁹ Rody, Y.¹⁰ Gardin, C.¹¹ Foussadier, F.¹² Shiavone, P.¹³

4
- 33745769470
- Microlithography World, November
- P. Martin, C. Progler, J. Wiley, "Fast RET verification in a box?" Microlithography World, November, 2005
- (2005) Fast RET Verification in A Box?
- Martin, P.¹ Progler, C.² Wiley, J.³

5
- 24644485285
- Design-based metrology: Advanced automation for CD-SEM recipe generation
- Richard M. Silver, Ed.
- C. Tabery, L. Capodieci, C. Haidinyak, K. Shah, M. Threefoot, B. Choo, B. Singh, Y. Nehmadi, C. Ofek, O. Menadeva, A. Ben-Porath, "Design-based metrology: advanced automation for CD-SEM recipe generation," Metrology, Inspection and Process Control for Microlithography XIX, Richard M. Silver, Ed., Vol. 5752, pp. 527-535, 2005
- (2005) Metrology, Inspection and Process Control for Microlithography XIX , vol.5752 , pp. 527-535
- Tabery, C.¹ Capodieci, L.² Haidinyak, C.³ Shah, K.⁴ Threefoot, M.⁵ Choo, B.⁶ Singh, B.⁷ Nehmadi, Y.⁸ Ofek, C.⁹ Menadeva, O.¹⁰ Ben-Porath, A.¹¹

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