Impact of line width roughness on device performance

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6152 I, Issue , 2006, Pages

  Lorusso, G F ^a   Leunissen, L H A ^a   Gustin, C ^a   Mercha, A ^a   Jurczak, M ^a   Marchman, H M ^b   Azordegan, A ^c  

^a IMEC   (Belgium)

^b PHOTRONICS INC   (United States)

^c KLA TENCOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; CONDITION MONITORING; MEASUREMENT THEORY; ONLINE SYSTEMS; PERFORMANCE; STATISTICAL METHODS;

DEVICE APPLICATIONS; LINEWIDTH ROUGHNESS (LWR); MATCHING TECHNIQUES; STATISTICAL FLUCTUATIONS;

SURFACE ROUGHNESS;

EID: 33745587759     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.656128     Document Type: Conference Paper

References (5)

1. L.H.A. Leunissen et al., "Full Spectral Analysis of Line Width Roughness", proc. of SPIE 5752, 499 (2005)
2. Marcel J.M. Pelgrom et al, "Matching properties of MOS Transistors", IEEE J. Solid-State Circuits, Vol. 24, 5, 1433 (1989)
3. L.H.A. Leunissen, W.G. Lawrence and M. Ercken, "Line edge roughness: Experimental Results related to a two-parameter model" Microelectron. Eng. 73-74, 265 (2004)
4. J. A. Croon, L. H. A. Leunissen, M. Jurczak, M. Benndorf, R. Rooyackers, K. Ronse, S. Decoutere, W. Sansen, and H. E. Maes, "Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield", Proc. ESSDERC, 227 (2003); Ph. D. Thesis Jeroen Croon, ISBN 90-5682-496-1
5. P. Oldiges, Q. Lin, K. Petrillo, M. Sanchez, M. Ieong, and M. Hargrove, "Modeling Line Edge Roughness Effects in sub 100 Namometer Gate Length Devices", Proc. SISPAD, 131-134 (2000)