5 GHz 32 b integer-execution core in 130 nm dual-VT CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue SUPPL., 2002, Pages 334-335+535

  Vangal, S ^a   Borkar, N ^a   Seligman, E ^a   Govindarajulu, V ^a   Erraguntla, V ^a   Wilson, H ^a   Pangal, A ^a   Veeramachaneni, V ^a   Anders, M ^a   Tschanz, J ^a   Ye, Y ^a   Somasekhar, D ^a   Bloechel, B ^a   Dermer, G ^a   Krishnamurthy, R ^a   Narendra, S ^a   Stan, M ^a   Thompson, S ^a   De, V ^a   Borkar, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY DISSIPATION; JITTER; LOGIC CIRCUITS; TRANSISTORS;

SEMI-DYNAMIC FLIP-FLOPS (SDFF);

CMOS INTEGRATED CIRCUITS;

EID: 0036224875     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)