QCA memory with parallel read/serial write: Design and analysis

IEE Proceedings: Circuits, Devices and Systems

Volumn 153, Issue 3, 2006, Pages 199-206

  Ottavi, M ^a   Pontarelli, S ^b   Vankamamidi, V ^a   Salsano, A ^b   Lombardi, F ^a  

^a Northeastern University   (United States)

^b UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BITS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL GEOMETRY; COMPUTER ARCHITECTURE; LOGIC CIRCUITS; STORAGE ALLOCATION (COMPUTER);

MEMORY-IN-MOTION PARADIGM; PARALLEL MEMORY; PARALLEL READ; QUANTUM-DOT CELLULAR AUTOMATA (QCA); SERIAL WRITE;

AUTOMATA THEORY;

EID: 33745295468     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20050094     Document Type: Article

References (18)

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