Problems in designing with QCAs: Layout = timing

International Journal of Circuit Theory and Applications

Volumn 29, Issue 1, 2001, Pages 49-62

  Niemier, Michael T ^a   Kogge, Peter M ^a  

^a University of Notre Dame   (United States)

Author keywords

Architecture; Circuit design; Processor dataflow; QCA; Quantum cellular automata

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; QUANTUM ELECTRONICS; VLSI CIRCUITS;

PROCESSOR DATAFLOW; QUANTUM CELLULAR AUTOMATON CIRCUIT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034766466     PISSN: 00989886     EISSN: None     Source Type: Journal    
DOI: 10.1002/1097-007X(200101/02)29:1<49::AID-CTA132>3.0.CO;2-1     Document Type: Article

References (4)

1. Digital logic gate using quantum-dot cellular automata
2. Experimental demonstration of a binary wire for quantum-dot cellular automata
3. A device architecture for computing with quantum dots
4. Logic in wire: Using quantum dots to implement a microprocessor