Energy-aware data prefetching for general-purpose programs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3471 LNCS, Issue , 2005, Pages 78-94

  Guo, Yao ^a   Chheda, Saurabh ^b   Koren, Israel ^a   Mani Krishna, C ^a   Moritz, Csaba Andras ^a  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b BlueRISC Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SOFTWARE; ENERGY EFFICIENCY; PERFORMANCE;

ENERGY ASPECT; HARDWARE-BASED DATA; MEMORY ACCESSES; PREFETCHING;

DATA PROCESSING;

EID: 33745159378     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11574859_6     Document Type: Conference Paper

References (20)

1. The standard performance evaluation corporation, 2000. http://www.spec.org.
2. N. Azizi, A. Moshovos, and F. N. Najm. Low-leakage asymmetric-cell sram. In Proc. of the 2002 international symposium on Low power electronics and design, pages 48-51, 2002.
3. J. L. Baer and T. F. Chen. An effictive on-chip preloading scheme to reduce data access penalty. In Supercomputing 1991, pages 179-186, Nov. 1991.
4. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, June 2000.
5. D. C. Burger and T. M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-1997-1342, University of Wisconsin, Madison, June 1997.
6. R. Cooksey, S. Jourdan, and D. Grunwald. A stateless content-directed data prefetching mechanism. In Tenth intl. conf. on architectural support for programming languages and operating systems(ASPLOS-X), pages 279-290, 2002.
7. M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the design of the alpha 21264 microprocessor. In Proceedings of the 1998 Conference on Design Automation (DAC-98), pages 726-731, June 1998.
8. Y. Guo, S. Chheda, I. Koren, C. M. Krishna, and C. A. Moritz. Energy characterization of hardware-based data prefetching. In International Conference on Computer Design (ICCD'04), Oct. 2004.
9. Y. Guo, S. Chheda, and C. A. Moritz. Runtime biased pointer reuse analysis and its application to energy efficiency. In Workshop on Power-Aware Computer Systems(PACS) at Micro-36, pages 1-15, Dec. 2003.
10. M. H. Lipasti, W. J. Schmidt, S. R. Kunkel, and R. R. Roediger. Spaid: software prefetching in pointer- and call-intensive environments. In Proceedings of the 28th annual international symposium on Microarchitecture, pages 231-236, Nov. 1995.
11. C.-K. Luk and T. C. Mowry. Compiler-based prefetching for recursive data structures. In Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), pages 222-233, Oct. 1996.
12. J. Montanaro and et. al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. Digital Technical Journal of Digital Equipment Corporation, 9(1), 1997.
13. T. Mowry. Tolerating Latency Through Software Controlled Data Prefetching. PhD thesis, Dept. of Computer Science, Stanford University, Mar. 1994.
14. T. C. Mowry, M. S. Lam, and A. Gupta. Design and evaluation of a compiler algorithm for prefetching. In Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 62-73, Oct. 1992.
15. A. Rogers, M. C. Carlisle, J. H. Reppy, and L. J. Hendren. Supporting dynamic data structures on distributed-memory machines. ACM Transactions on Programming Languages and Systems, 17(2):233-263, Mar. 1995.
16. A. Roth, A. Moshovos, and G. S. Sohi. Dependence based prefetching for linked data structures. In Proc. of the 8th Architectural Support for Programming Languages and Operating Systems), pages 115-126, oct 1998.
17. A. Roth and G. S. Sohi. Effective jump-pointer prefetching for linked data structures. In Proceedings of the 26th annual international symposium on Computer architecture, pages 111-121. IEEE Computer Society Press, 1999.
18. A. J. Smith. Sequential program prefetching in memory hierarchies. IEEE Computer, 11(12):7-21, Dec. 1978.
19. R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjiang, S.-W. Liao, C.-W. Tseng, M. W. Hall, M. Lam, and J. L. Henriessy. SUIF: A parallelizing and optimizing research compiler. Technical Report CSL-TR-94-620, Computer Systems Laboratory, Stanford University, May 1994.
20. M. Zhang and K. Asanovic. Highly-associative caches for low-power processors. In Kool Chips Workshop, 33rd International Symposium on Microarchitecture, Dec. 2000.