An area-efficient PLL architecture in 90-nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 48-49

  Lim, Peter J ^a  

^a NVIDIA   (United States)

Author keywords

Charge pump; Clock synthesizer; DLL; Gate leakage; PLL

Indexed keywords

CAPACITANCE; CAPACITORS; ELECTRIC FILTERS; FREQUENCY SYNTHESIZERS; PHASE LOCKED LOOPS;

CHARGE PUMPS; CLOCK SYNTHESIZERS; DLL; GATE LEAKAGE;

CMOS INTEGRATED CIRCUITS;

EID: 33745155459     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469330     Document Type: Conference Paper

References (6)

1. Roberto Aparicio, All Hajimiri, "Capacity limits and matching properties of integrated capacitors", IEEE Journal of Solid-State Circuits, vol. 37, no. 3, March 2002, pp. 384-393.
2. Stefanos Sidiropoulos, Dean Liu, Jaeha Kim, Guyeon Wei, and Mark Horowitz, "Adaptive bandwidth DLL's and PLL's using regulated supply CMOS buffers", 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 124-127.
3. Tai-Cheng Lee and Behzad Razavi, "A stabilization technique for phase-locked frequency synthesizers" IEEE Journal of Solid-State Circuits, vol. 38, no. 6, June 2003, pp. 888-894.
4. John G. Maneatis, " Low-jitter process-independent DLL and PLL based on self-biased techniques" IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
5. Adrian Maxim, Baker Scott, Ed Schneider, Melvin Hagge, Steve Chacko, Dan Stiurca, "A low jitter 125-1250 MHz process independent 0.18um CMOS PLL based on a sample-reset loop filter", ISSCC 2001 Digest of Technical Papers, pp. 394-395.
6. John G. Maneatis, Jaeha Kim, lain McClatchie, Jay Maxey, Manjusha Shankaradas, "Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL", ISSCC 2003 Digest of Technical Papers, pp. 424-425.