Notice of Removal: A - 86dBc reference spurs 1-5GHz 0.13?m CMOS PLL using a dual-path sampled loop filter architecture

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 248-251

  Maxim, Adrian ^a  

^a Cirrus Logic   (United States)

Author keywords

Charge pump; Frequency synthesizer; Phase noise; PLL; Reference spurs; Ring oscillator; Sampled filter

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FILTERS; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC); SPURIOUS SIGNAL NOISE;

CHARGE-PUMP; FREQUENCY SYNTHESIZER; REFERENCE SPURS; RING OSCILLATOR; SAMPLED FILTER;

PHASE LOCKED LOOPS;

EID: 33745130435     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469378     Document Type: TB

References (6)

1. A. Maxim, "A 160-2550MHz CMOS Active Clock Deskewing PLL Using Analog Phase Interpolation", ISSCC Dig. Tech. Papers, Feb. 204, pp 424-425
2. Y. Koo, et al., "A fully integrated CMOS frequency synthesizer with charge-averaging charge-pump and dual-path loop filter for PCS systems", IEEE J.Solid-State Circuits, vol.37, pp.536-542, May 2002
3. A Maxim, el al., "A low jitter 125-1250 MHz process independent 0.18μm CMOS PLL based on a sample-reset loop filter", ISSCC Dig. Tech. Papers, Feb. 2001, pp 394-395.
4. J. Manealis, el al., "Self-biased, high bandwidth, low jitter 1 to 4096 multiplier PLL", ISSCC Dig. Tech. Papers. Feb. 2003, pp 424-425.
5. T. Lee, B. Razavi, "A stabilization technique for phase-locked frequency synthesizers", IEEE J. Solid-State Circuits, vol.38, pp.888-894. June 2003.
6. B. Muer, M. Steyaert, "A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800". J.Solid-State Circuits, vol.37. pp.835-844. Feb.2002.