Design flow on a chip - An evolvable HW/SW platform

Proceedings - Second International Conference on Autonomic Computing, ICAC 2005

Volumn 2005, Issue , 2005, Pages 393-394

  Kubisch, Stephan ^a   Hecht, Ronald ^a   Timmermann, Dirk ^a  

^a UNIVERSITY OF ROSTOCK   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33744936144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICAC.2005.22     Document Type: Conference Paper

References (4)

1. G. Brebner. A virtual hardware operating system for the Xilinx XC6200. In LNCS, volume 1142, 1996.
2. G. Brebner and O. Diessel. Chip-Based Reconfigurable Task Management. In LNCS, volume 2147, 2001.
3. W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. of the Design Automation Conference, 2001.
4. R. Hecht, D. Timmermann, S. Kubisch, and E. Zeeb. Network-on-Chip basierte Laufzeitsysteme fuer dynamisch konfigurierbare Hardware. In ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26 2004.