Speed enhancement of a class of digital phase locked loops (DPLLs) by dynamic gain control technique

AEU - International Journal of Electronics and Communications

Volumn 60, Issue 7, 2006, Pages 539-544

  Sarkar, Bishnu Charan ^a   Banerjee, Tanmoy ^a  

^a UNIVERSITY OF BURDWAN   (India)

Author keywords

Digital phase locked loop (DPLL); Stability criteria; Transient behaviour

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; GAIN CONTROL; NUMERICAL METHODS; PERFORMANCE; STABILITY CRITERIA;

CONTROL TECHNIQUE; DIGITAL PHASE LOCKED LOOP (DPLL); DYNAMIC GAIN; TRANSIENT BEHAVIOUR;

PHASE LOCKED LOOPS;

EID: 33744822773     PISSN: 14348411     EISSN: 16180399     Source Type: Journal    
DOI: 10.1016/j.aeue.2005.10.016     Document Type: Article

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