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Volumn 145, Issue 2-5, 1998, Pages 71-77

Quaternary voltage-mode CMOS circuits for multiple-valued logic

Author keywords

CMOS circuits; Multiple valued logic

Indexed keywords

COMPUTER SIMULATION; DIGITAL ARITHMETIC; LOGIC CIRCUITS; MOSFET DEVICES;

EID: 0032050210     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19981763     Document Type: Article
Times cited : (27)

References (17)
  • 1
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    • Hurst, S.L.1
  • 2
    • 0023994762 scopus 로고
    • Comparison of binary and multivalued ICs according to VLSI criteria
    • April
    • ETIEMBLE, D., and ISRAEL, M.: 'Comparison of binary and multivalued ICs according to VLSI criteria', IEEE Comput. Mag., April 1988, pp. 28-42
    • (1988) IEEE Comput. Mag. , pp. 28-42
    • Etiemble, D.1    Israel, M.2
  • 4
    • 0001757896 scopus 로고
    • A 32 × 32-bit multiplier using multiple-valued MOS current-mode circuits
    • KAWAHITO, S., KAMEYAMA, M., HIGUCHI, T., and YAMADA, H.: 'A 32 × 32-bit multiplier using multiple-valued MOS current-mode circuits', IEEE J. Solid-State Circ., 1988, 23, (1), pp. 124-132
    • (1988) IEEE J. Solid-State Circ. , vol.23 , Issue.1 , pp. 124-132
    • Kawahito, S.1    Kameyama, M.2    Higuchi, T.3    Yamada, H.4
  • 6
    • 0023399140 scopus 로고
    • New logical-sum and logical-product circuits using CMOS transistors and their applications to four-valued combinational circuits
    • WATANABE, T., MATSUMOTO, M., and LI, T.: 'New logical-sum and logical-product circuits using CMOS transistors and their applications to four-valued combinational circuits', Int. J. Electron., 1987, 63, (2), pp. 215-227
    • (1987) Int. J. Electron. , vol.63 , Issue.2 , pp. 215-227
    • Watanabe, T.1    Matsumoto, M.2    Li, T.3
  • 9
    • 0021404263 scopus 로고
    • Depletion/enhancement CMOS for a low power family of three-valued logic circuits
    • HEUNG, A., and MOUFTAH, H.T.: 'Depletion/enhancement CMOS for a low power family of three-valued logic circuits', IEEE J. Solid-State Circ., 1985, SC-20, (2), pp. 609-616
    • (1985) IEEE J. Solid-State Circ. , vol.SC-20 , Issue.2 , pp. 609-616
    • Heung, A.1    Mouftah, H.T.2
  • 13
    • 0022665606 scopus 로고
    • Characteristics of prototype CMOS quaternary logic encoder-decoder circuits
    • MANGIN, J.L., and CURRENT, K.W.: 'Characteristics of prototype CMOS quaternary logic encoder-decoder circuits', IEEE Trans. Comput., 1986, C-35, (2), pp. 157-161
    • (1986) IEEE Trans. Comput. , vol.C-35 , Issue.2 , pp. 157-161
    • Mangin, J.L.1    Current, K.W.2
  • 14
    • 0030126932 scopus 로고    scopus 로고
    • Ternary latches for TDDNL pipelined systems
    • HERRFELD, A., and HENTSCHKE, S.: 'Ternary latches for TDDNL pipelined systems', Int. J. Electron., 1996, 80, (4), pp. 547-560
    • (1996) Int. J. Electron. , vol.80 , Issue.4 , pp. 547-560
    • Herrfeld, A.1    Hentschke, S.2
  • 15
    • 0028548681 scopus 로고
    • Voltage-mode CMOS quaternary latch circuit
    • CURRENT, K.W.: 'Voltage-mode CMOS quaternary latch circuit'. Electron. Lett., 1994, 30, (23), pp. 1928-1929
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    • Current, K.W.1
  • 16
    • 0029276518 scopus 로고
    • Multiple-valued logic memory circuit
    • CURRENT, K.W.: 'Multiple-valued logic memory circuit', Int. J. Electron., 1995, 78, (3), pp. 547-555
    • (1995) Int. J. Electron. , vol.78 , Issue.3 , pp. 547-555
    • Current, K.W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.