Plasma etching of tapered features in silicon for MEMS and wafer level packaging applications

Journal of Physics: Conference Series

Volumn 34, Issue 1, 2006, Pages 271-276

  Ngo, Ha Duong ^a   Hiess, Andre ^a   Seidemann, Volker ^a   Studzinski, Daniel ^a   Lange, Martin ^a   Leib, Jürgen ^a   Shariff, Dzafir ^b   Ashraf, Huma ^c   Steel, Mike ^c   Atabo, Lilian ^c   Reast, Jon ^c  

^a SCHOTT Electronics Packaging GmbH   (Germany)

^b SCHOTT Advanced Packaging Singapore Pte Ltd   (Singapore)

^c Surface Technology Systems plc   (United Kingdom)

Author keywords

DRIE; MEMS; Plasma Etch; Tapered silicon profile; Wafer Level Packaging

Indexed keywords

EID: 33744540250     PISSN: 17426588     EISSN: 17426596     Source Type: Conference Proceeding    
DOI: 10.1088/1742-6596/34/1/045     Document Type: Article

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